SLVSES4C September   2019  – June 2021 TPS54J060

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Internal LDO
      2. 7.3.2  Split Rail and External LDO
      3. 7.3.3  Output Voltage Setting
      4. 7.3.4  Soft Start and Output-Voltage Tracking
      5. 7.3.5  Frequency and Operation Mode Selection
      6. 7.3.6  D-CAP3 Control
      7. 7.3.7  Current Sense and Positive Overcurrent Protection
      8. 7.3.8  Low-side FET Negative Current Limit
      9. 7.3.9  Power Good
      10. 7.3.10 Overvoltage and Undervoltage Protection
      11. 7.3.11 Out-Of-Bounds Operation (OOB)
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Pre-Bias Start-up
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 8.2.2.2  Choose the Output Inductor (L)
        3. 8.2.2.3  Set the Current Limit (TRIP)
        4. 8.2.2.4  Choose the Output Capacitors (COUT)
        5. 8.2.2.5  Choose the Input Capacitors (CIN)
        6. 8.2.2.6  Feedback Network (FB Pin)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 Series BOOT Resistor and RC Snubber
        12. 8.2.2.12 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Glossary
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Ordering Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.6 Feedback Network (FB Pin)

The output voltage is programmed by the voltage-divider resistors, RFB_T and RFB_B, shown in Equation 25. Connect RFB_T between the FB pin and the output, and connect RFB_B between the FB pin and AGND. The recommended RFB_B value is from 499 Ω to 20 kΩ. Determine RFB_T using Equation 25.

Equation 25. GUID-750842E9-2F45-4A29-973F-31C31FE661FB-low.gif

In most applications, a feedforward capacitor (CFF) in parallel with RFB_T is recommended. CFF can improve the transient response and increase the phase margin. CFF can be required for sufficient phase margin if the output voltage is greater than 1.8 V or if the LC double pole frequency is below fSW / 60. The frequency of the LC double pole for this application is calculated with Equation 26 to be 12.1 kHz. This is less than fSW / 60 so CFF is used.

Equation 26. GUID-33B2A143-866B-4DF1-B2CD-69E5D2BE7AF2-low.gif

The recommended value for CFF is calculated with Equation 27. This equation selects CFF to put a zero at fLC × 3. In this example, the calculated value is 434 pF and a standard value of 470 pF is used. For higher output voltages, the zero from CFF should be closer to the LC double pole. For example, for a 5-V application, the zero from CFF should be placed at or even below the LC double pole.

Equation 27. GUID-4AD3439A-A6A1-499C-8E67-E2EEAE8B5FCD-low.gif