The TPS54J060 requires input bypass capacitors between the VIN and PGND pins to bypass the power-stage. The bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At least 10 µF of ceramic capacitance and a 0.01-µF to 0.1-µF high frequency ceramic bypass capacitor is required. The high frequency bypass capacitor minimizes high frequency voltage overshoot across the power-stage. The ceramic capacitors must be high-quality dielectric of X5R or X7R for their high capacitance-to-volume ratio and stable characteristics across temperature. In addition to this, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions.

The input capacitance required to meet a specific input ripple target can be calculated with Equation 23. A recommended target input voltage ripple is 5% the minimum input voltage, 400 mV in this example. The calculated input capacitance is 2.4 µF and the minimum input capacitance of 10 µF exceeds this. This example meets these two requirements with two 4.7-µF 0603 25-V ceramic capacitors and two 10-µF 1206 25-V ceramic capacitors.

Equation 23.

The capacitor must also have an RMS current rating greater than the maximum input RMS current in the application. The input RMS current the input capacitors must support is calculated by Equation 24 and is 2.5 A in this example. The ceramic input capacitors have a current rating much greater than this.

Equation 24.

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, the selection process in this article is recommended.