SLVSES4C September   2019  – June 2021 TPS54J060

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Internal LDO
      2. 7.3.2  Split Rail and External LDO
      3. 7.3.3  Output Voltage Setting
      4. 7.3.4  Soft Start and Output-Voltage Tracking
      5. 7.3.5  Frequency and Operation Mode Selection
      6. 7.3.6  D-CAP3 Control
      7. 7.3.7  Current Sense and Positive Overcurrent Protection
      8. 7.3.8  Low-side FET Negative Current Limit
      9. 7.3.9  Power Good
      10. 7.3.10 Overvoltage and Undervoltage Protection
      11. 7.3.11 Out-Of-Bounds Operation (OOB)
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Pre-Bias Start-up
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 8.2.2.2  Choose the Output Inductor (L)
        3. 8.2.2.3  Set the Current Limit (TRIP)
        4. 8.2.2.4  Choose the Output Capacitors (COUT)
        5. 8.2.2.5  Choose the Input Capacitors (CIN)
        6. 8.2.2.6  Feedback Network (FB Pin)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 Series BOOT Resistor and RC Snubber
        12. 8.2.2.12 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Glossary
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Ordering Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.1 Choose the Switching Frequency and Operation Mode (MODE Pin)

The switching frequency and light load mode of operation are configured by the resistor on the MODE pin. From Table 7-1, the MODE pin is connected to VCC to set a 1100-kHz switching frequency with discontinuous conduction mode and skip mode enabled at light loads.

When selecting the switching frequency of a buck converter, the minimum on-time and minimum off-time must be considered. Equation 6 calculates the maximum fSW before being limited by the minimum on-time. When hitting the minimum on-time limits of a converter with D-CAP3 control, the effective switching frequency will change to keep the output voltage regulated. This calculation ignores resistive drops in the converter to give a worst case estimation.

Equation 6. GUID-E9B2C695-E9BB-43D7-9B49-B4600DE08ADB-low.gif

Equation 7 calculates the maximum fSW before being limited by the minimum off-time. When hitting the minimum off-time limits of a converter with D-CAP3 control, the operating duty cycle will max out and the output voltage will begin to drop with the input voltage. This equation requires the DC resistance of the inductor, RDCR, selected in the following step so this preliminary calculation assumes a resistance of 10 mΩ. If you are operating near the maximum fSW limited by the minimum off-time, the variation in resistance across temperature must be considered when using Equation 7. The selected fSW of 1100 kHz is below the two calculated maximum values.

Equation 7. GUID-4700242F-07F6-42C9-9C62-4C982E66B468-low.gif