SLVSI31 April   2026 TPS61371

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Lockout
      2. 6.3.2  Enable and Disable
      3. 6.3.3  Output Voltage Setting
      4. 6.3.4  Reference Voltage Slew Rate
      5. 6.3.5  Error Amplifier
      6. 6.3.6  Bootstrap Voltage (BST)
      7. 6.3.7  Load Disconnect
      8. 6.3.8  Output Discharge
      9. 6.3.9  Overvoltage Protection
      10. 6.3.10 Thermal Shutdown
      11. 6.3.11 Start-Up
      12. 6.3.12 Short Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation
      2. 6.4.2 Auto PFM Mode
      3. 6.4.3 Forced PWM Mode
      4. 6.4.4 Mode Selectable
    5. 6.5 Programming
      1. 6.5.1 Serial Interface Description
      2. 6.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 6.5.3 I2C Update Sequence
      4. 6.5.4 I2C Target Address
        1. 6.5.4.1 I2C Target Address Description
  8. 7 Register Map
    1. 7.1 Register Description
      1. 7.1.1 Register Map
      2. 7.1.2 Register CONTROL (Register address: 0x01; Default: 0x01)
      3. 7.1.3 Register VOUT (Register address: 0x02; Default: 0x36)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Selecting the Inductor
        3. 8.2.2.3 Selecting the Output Capacitors
        4. 8.2.2.4 Selecting the Input Capacitors
        5. 8.2.2.5 Loop Stability and Compensation
          1. 8.2.2.5.1 Small Signal Model
        6. 8.2.2.6 Loop Compensation Design Steps
        7. 8.2.2.7 Selecting the Bootstrap Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.2 Register CONTROL (Register address: 0x01; Default: 0x01)

Return to Register Map

Table 7-2 Register CONTROL Format
7 6 5 4 3 2 1 0
NIL[1:0] FPWM REFERENCE SLEW RATE DISCHARGE DELAY TIME DISCHARGE_VOUT CONVERTER_EN
R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only
Table 7-3 Register CONTROL Field Descriptions
Bit Field Type Reset Description
7 NIL[1:0] R 0b00

Not used.

During write operations data for these bits are ignored. During read operations 0 is returned
6 FPWM R/W 0b0 Set device work mode ('OR'ed with MODE-pin)

0: Auto PFM mode if MODE pin is logic low.

1: Forced PWM mode if MODE pin is logic low.

If MODE pin is high, the device always works in Forced PWM mode
5 REFERENCE SLEW RATE R/W 0b0 Vref slew rate

0: Slew Rate 0, 3.96mV/10µs

1: Slew Rate 1, 6.60mV/10µs
4:3 DISCHARGE DELAY TIME R/W 0b00

Delay time of VOUT discharge

00: 50µs

01: 100µs

10: 150µs

11: 200µs
2:1 DISCHARGE _VOUT R/W 0b00 Set the VOUT discharge resistance

00: DISABLE

01: 100Ω

10 or 11: 300Ω
0 CONVERTER_EN R/W 0b1 Enable converter ('AND'ed with EN-pin)

0: DISABLE

1: ENABLE