SLVSEK4C July   2019  – February 2020 TPS63810 , TPS63811

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Output Current
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     BGA Package (YFF) Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Scheme
        1. 8.3.1.1 Buck Operation
        2. 8.3.1.2 Boost Operation
        3. 8.3.1.3 Buck-Boost Operation
      2. 8.3.2  Control Scheme
      3. 8.3.3  Power-Save Mode Operation (PSM)
      4. 8.3.4  Forced-PWM Operation (FPWM)
      5. 8.3.5  Ramp-PWM Operation (RPWM)
      6. 8.3.6  Device Enable (EN)
      7. 8.3.7  Undervoltage Lockout (UVLO)
      8. 8.3.8  Soft Start
      9. 8.3.9  Output Voltage Control
        1. 8.3.9.1 Dynamic Voltage Scaling
      10. 8.3.10 Protection Functions
        1. 8.3.10.1 Input Voltage Protection (IVP)
        2. 8.3.10.2 Current Limit Mode and Overcurrent Protection
        3. 8.3.10.3 Thermal Shutdown
      11. 8.3.11 Power Good
      12. 8.3.12 Load Disconnect
      13. 8.3.13 Output Discharge
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL (Slave address: 0b1110101; Register address: 0x01; Default: 0x00 or 0x20)
          1. Table 3. Register CONTROL Field Descriptions
        3. 8.6.1.3 Register STATUS (Slave address: 0b1110101; Register address: 0x02; Default: 0x00)
          1. Table 4. Register STATUS Field Descriptions
        4. 8.6.1.4 Register DEVID (Slave address: 0b1110101; Register address: 0x03; Default: 0x04)
          1. Table 5. Register DEVID Field Descriptions
        5. 8.6.1.5 Register VOUT1 (Slave address: 0b1110101; Register address: 0x04; Default: 0x3C)
          1. Table 6. Register VOUT1 Field Descriptions
        6. 8.6.1.6 Register VOUT2 (Slave address: 0b1110101; Register address: 0x05; Default: 0x42)
          1. Table 7. Register VOUT2 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 1.8-V to 5.2-V Output Smartphone Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Capacitor Selection
          2. 9.2.1.2.2 Inductor Selection
          3. 9.2.1.2.3 Output Capacitor Selection
          4. 9.2.1.2.4 I2C Pullup Resistor Selection
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Support Resources
    6. 12.6 Trademarks
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 Control Scheme

The device uses a constant off-time, peak-current-mode control scheme where an outer voltage control loop generates the demand signal for an inner current control loop. During the on-time, the inner current control loop monitors the inductor current, and when the inductor current equals the demand signal from the error amplifier, the on-time stops and the next part of the switching cycle starts.

The off-time is a function of VI and VO and the operating mode (buck, boost, or buck-boost) of the converter.

TPS63810 TPS63811 dwg-12-slvsek4.gifFigure 7. Peak Current Control (Buck and Boost Operation)
TPS63810 TPS63811 dwg-09-slvsek4.gifFigure 8. Peak Current Control – Buck-Boost Operation with VI < VO
TPS63810 TPS63811 dwg-10-slvsek4.gifFigure 9. Peak Current Control – Buck-Boost Operation with VI > VO
TPS63810 TPS63811 dwg-11-slvsek4.gifFigure 10. Peak Current Control – Buck-Boost Operation with VI = VO

During PWM operation, current can flow in the reverse direction (from output to input). In this case, the error amplifier provides a negative peak current target. Note that the average reverse current is greater (more negative) than the peak current (see Figure 11 and Figure 12).

TPS63810 TPS63811 dwg-13-slvsek4.gifFigure 11. Reverse Peak Current Control – Buck and Boost Operation
TPS63810 TPS63811 dwg-14-slvsek4.gifFigure 12. Reverse Peak Current Control – Buck-Boost Operation, with VI > VO