SLDS234B December   2017  – September 2018 TPS65218D0

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Simplified Schematic
  2. 2 Revision History
  3. 3 Pin Configuration and Functions
    1. 3.1 Pin Functions
      1.      Pin Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Wake-Up and Power-Up and Power-Down Sequencing
        1. 5.3.1.1  Power-Up Sequencing
        2. 5.3.1.2  Power-Down Sequencing
        3. 5.3.1.3  Strobes 1 and 2
        4. 5.3.1.4  Supply Voltage Supervisor and Power Good (PGOOD)
        5. 5.3.1.5  Backup Supply Power-Good (PGOOD_BU)
        6. 5.3.1.6  Internal LDO (INT_LDO)
        7. 5.3.1.7  Current Limited Load Switches
          1. 5.3.1.7.1 Load Switch 1 (LS1)
          2. 5.3.1.7.2 Load Switch 2 (LS2)
          3. 5.3.1.7.3 Load Switch 3 (LS3)
        8. 5.3.1.8  LDO1
        9. 5.3.1.9  Coin Cell Battery Voltage Acquisition
        10. 5.3.1.10 UVLO
        11. 5.3.1.11 Power-Fail Comparator
        12. 5.3.1.12 Battery-Backup Supply Power-Path
        13. 5.3.1.13 DCDC3 / DCDC4 Power-Up Default Selection
        14. 5.3.1.14 I/O Configuration
          1. 5.3.1.14.1 Configuring GPO2 as Open-Drain Output
          2. 5.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
        15. 5.3.1.15 Push Button Input (PB)
          1. 5.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
          2. 5.3.1.15.2 Push Button Reset
        16. 5.3.1.16 AC_DET Input (AC_DET)
        17. 5.3.1.17 Interrupt Pin (INT)
        18. 5.3.1.18 I2C Bus Operation
    4. 5.4 Device Functional Modes
      1. 5.4.1 Modes of Operation
      2. 5.4.2 OFF
      3. 5.4.3 ACTIVE
      4. 5.4.4 SUSPEND
      5. 5.4.5 RESET
    5. 5.5 Programming
      1. 5.5.1 Programming Power-Up Default Values
    6. 5.6 Register Maps
      1. 5.6.1 Password Protection
      2. 5.6.2 Freshness Seal (FSEAL) Bit
      3. 5.6.3 FLAG Register
      4. 5.6.4 TPS65218D0 Registers
        1. 5.6.4.1  CHIPID Register (subaddress = 0x0) [reset = 0x5]
          1. Table 5-8 CHIPID Register Field Descriptions
        2. 5.6.4.2  INT1 Register (subaddress = 0x1) [reset = 0x0]
          1. Table 5-9 INT1 Register Field Descriptions
        3. 5.6.4.3  INT2 Register (subaddress = 0x2) [reset = 0x0]
          1. Table 5-10 INT2 Register Field Descriptions
        4. 5.6.4.4  INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
          1. Table 5-11 INT_MASK1 Register Field Descriptions
        5. 5.6.4.5  INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
          1. Table 5-12 INT_MASK2 Register Field Descriptions
        6. 5.6.4.6  STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
          1. Table 5-13 STATUS Register Field Descriptions
        7. 5.6.4.7  CONTROL Register (subaddress = 0x6) [reset = 0x0]
          1. Table 5-14 CONTROL Register Field Descriptions
        8. 5.6.4.8  FLAG Register (subaddress = 0x7) [reset = 0x0]
          1. Table 5-15 FLAG Register Field Descriptions
        9. 5.6.4.9  PASSWORD Register (subaddress = 0x10) [reset = 0x0]
          1. Table 5-16 PASSWORD Register Field Descriptions
        10. 5.6.4.10 ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
          1. Table 5-17 ENABLE1 Register Field Descriptions
        11. 5.6.4.11 ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
          1. Table 5-18 ENABLE2 Register Field Descriptions
        12. 5.6.4.12 CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
          1. Table 5-19 CONFIG1 Register Field Descriptions
        13. 5.6.4.13 CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
          1. Table 5-20 CONFIG2 Register Field Descriptions
        14. 5.6.4.14 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
          1. Table 5-21 CONFIG3 Register Field Descriptions
        15. 5.6.4.15 DCDC1 Register (offset = 0x16) [reset = 0x99]
          1. Table 5-22 DCDC1 Register Field Descriptions
        16. 5.6.4.16 DCDC2 Register (subaddress = 0x17) [reset = 0x99]
          1. Table 5-23 DCDC2 Register Field Descriptions
        17. 5.6.4.17 DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
          1. Table 5-24 DCDC3 Register Field Descriptions
        18. 5.6.4.18 DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
          1. Table 5-25 DCDC4 Register Field Descriptions
        19. 5.6.4.19 SLEW Register (subaddress = 0x1A) [reset = 0x6]
          1. Table 5-26 SLEW Register Field Descriptions
        20. 5.6.4.20 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
          1. Table 5-27 LDO1 Register Field Descriptions
        21. 5.6.4.21 SEQ1 Register (subaddress = 0x20) [reset = 0x0]
          1. Table 5-28 SEQ1 Register Field Descriptions
        22. 5.6.4.22 SEQ2 Register (subaddress = 0x21) [reset = 0x0]
          1. Table 5-29 SEQ2 Register Field Descriptions
        23. 5.6.4.23 SEQ3 Register (subaddress = 0x22) [reset = 0x98]
          1. Table 5-30 SEQ3 Register Field Descriptions
        24. 5.6.4.24 SEQ4 Register (subaddress = 0x23) [reset = 0x75]
          1. Table 5-31 SEQ4 Register Field Descriptions
        25. 5.6.4.25 SEQ5 Register (subaddress = 0x24) [reset = 0x12]
          1. Table 5-32 SEQ5 Register Field Descriptions
        26. 5.6.4.26 SEQ6 Register (subaddress = 0x25) [reset = 0x63]
          1. Table 5-33 SEQ6 Register Field Descriptions
        27. 5.6.4.27 SEQ7 Register (subaddress = 0x26) [reset = 0x3]
          1. Table 5-34 SEQ7 Register Field Descriptions
  6. 6 Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Applications Without Backup Battery
      2. 6.1.2 Applications Without Battery Backup Supplies
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 Output Filter Design
        2. 6.2.2.2 Inductor Selection for Buck Converters
        3. 6.2.2.3 Output Capacitor Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Community Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE AND CURRENTS
VIN_BIAS Input supply voltage range Normal operation 2.7 5.5 V
EEPROM programming 4.5 5.5
VUVLO Hysteresis Supply rising UVLOHYS = 0b 200 mV
UVLOHYS = 1b 400 mV
Deglitch time 5 ms
IOFF OFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LSx, IN_BU VIN = 3.6 V; All rails disabled.
TJ = 0°C to 85°C 		5 µA
ISUSPEND SUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LSx, IN_BU VIN = 3.6 V; DCDC3 enabled, low-power mode, no load.
All other rails disabled.
TJ = 0°C to 105°C 		220 µA
SYS_BU
VSYS_BU SYS_BU voltage range Powered from VIN_BU or VCC 2.2 5.5 V
CSYS_BU Recommended SYS_BU capacitor Ceramic, X5R or X7R, see Table 6-3 1 µF
Tolerance Ceramic, X5R or X7R, rated voltage ≥ 6.3 V –20% 20%
INT_LDO
VINT_LDO Output voltage 2.5 V
DC accuracy IOUT < 10 mA –2% 2%
IOUT Output current range Maximum allowable external load 0 10 mA
ILIMIT Short circuit current limit Output shorted to GND 23 mA
tHOLD Hold-up time Measured from VINT_LDO = 2.3 V to VINT_LDO = 1.8 V
All rails enabled before power off,
IN_BIAS tied to IN_DCDC1-4, IN_LDO1
VIN_BIAS = 2.8 V to 0 V in < 5 µs
No external load on INT_LDO
CINT_LDO = 1 µF, see Table 6-3 		150 ms
COUT Nominal output capacitor value Ceramic, X5R or X7R, see Table 6-3 0.1 1 22 µF
Tolerance Ceramic, X5R or X7R, rated voltage ≥ 6.3 V –20% 20%
DCDC1 (1.1-V BUCK)
VIN_DCDC1 Input voltage range VIN_BIAS > VUVLO 2.7 5.5 V
VDCDC1 Output voltage range Adjustable through I2C 0.85 1.675 V
DC accuracy 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range		 –2.5% 2.5%
IOUT Continuous output current VIN_DCDC1 > 2.7 V 1.8 A
IQ Quiescent current Total current from IN_DCDC1 pin; Device not switching, no load 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC1 = 3.6 V 230 355 mΩ
Low-side FET on resistance VIN_DCDC1 = 3.6 V 90 145
ILIMIT High-side current limit VIN_DCDC1 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC1 = 3.6 V 3.1
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 96% 96.5% 97%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC1 and after DCDC1 register write (register 0x16) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 103% 103.5% 104%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2 1 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100(8) µF
DCDC2 (1.1-V BUCK)
VIN_DCDC2 Input voltage range VIN_BIAS > VUVLO 2.7 5.5 V
VDCDC2 Output voltage range Adjustable through I2C 0.85 1.675 V
DC accuracy 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range		 –2.5% 2.5%
IOUT Continuous output current VIN_DCDC2 > 2.7 V 1.8 A
IQ Quiescent current Total current from IN_DCDC2 pin; Device not switching, no load 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC2 = 3.6 V 230 355 mΩ
Low-side FET on resistance VIN_DCDC2 = 3.6 V 90 145
ILIMIT High-side current limit VIN_DCDC2 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC2 = 3.6 V 3.1
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 96% 96.5% 97%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC2 and after DCDC2 register write (register 0x17) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 103% 103.5% 104%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2 1 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100(8) µF
DCDC3 (1.2-V BUCK)
VIN_DCDC3 Input voltage range VIN_BIAS > VUVLO 2.7 5.5 V
VDCDC3 Output voltage range Adjustable through I2C 0.9 3.4 V
DC accuracy 2.7 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 1.8 A,
VIN_DCDC3 ≥ (VDCDC3 + 700 mV)		 –2% 2%
Dynamic accuracy In respect to nominal output voltage
IOUT = 50 mA to 450 mA in < 1 µs
COUT ≥ 10 µF, over full input voltage range		 –2.5% –2.5%
IOUT Continuous output current VIN_DCDC3 > 2.7 V 1.8 A
IQ Quiescent current Total current from IN_DCDC3 pin;
Device not switching, no load		 25 50 µA
RDS(ON) High-side FET on resistance VIN_DCDC3 = 3.6 V 230 345 mΩ
Low-side FET on resistance VIN_DCDC3 = 3.6 V 100 150
ILIMIT High-side current limit VIN_DCDC3 = 3.6 V 2.8 A
Low-side current limit VIN_DCDC3 = 3.6 V 3
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC3 and after DCDC3 register write (register 0x18) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2 1.0 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 22 100 µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
VIN_DCDC4 Input voltage operating range VIN_BIAS > VUVLO, –40°C to +105°C 2.8 5.5 V
VDCDC4 Output voltage range Adjustable through I2C 1.175 3.4 V
VDCDC4 DC accuracy 4.2 V ≤ VIN ≤ 5.5 V;
3 V < VOUT ≤ 3.4 V
0 A ≤ IOUT ≤ 1.6 A 		–2% 2%
3.3 V ≤ VIN ≤ 4.2 V;
3 V < VOUT ≤ 3.4 V
0 A ≤ IOUT ≤ 1.3 A		 –2% 2%
2.8 V ≤ VIN ≤ 3.3 V;
3 V < VOUT ≤ 3.4 V
0 A ≤ IOUT ≤ 1 A		 –2% 2%
2.8 V ≤ VIN ≤ 5.5 V;
1.65 V < VOUT ≤ 3 V
0 A ≤ IOUT ≤ 1 A		 –2% 2%
2.8 V ≤ VIN ≤ 5.5 V;
1.175 V < VOUT ≤ 1.65 V
0 A ≤ IOUT ≤ 1 A		 –2.5% 2.5%
Output voltage ripple PFM mode enabled;
4.2 V ≤ VIN ≤ 5.5 V;
0 A ≤ IOUT ≤ 1.6 A
VOUT = 3.3 V		 150 mVpp
Minimum duty cycle in step-down mode 18%
IOUT Continuous output current VIN_DCDC4 = 2.8 V, VOUT = 3.3 V 1 A
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V 1.3
VIN_DCDC4 = 5 V, VOUT = 3.3 V 1.6
IQ Quiescent current Total current from IN_DCDC4 pin; Device not switching, no load 25 50 µA
fSW Switching frequency 2400 kHz
RDS(ON) High-side FET on resistance VIN_DCDC3 = 3.6 V IN_DCDC4 to L4A 166 mΩ
L4B to DCDC4 149
Low-side FET on resistance VIN_DCDC3 = 3.6 V L4A to GND 142 190
L4B to GND 144 190
ILIMIT Average switch current limit VIN_DCDC4 = 3.6 V 3000 mA
VPG Power-good threshold VOUT falling STRICT = 0b 88.5% 90% 91.5%
STRICT = 1b 95% 95.5% 96%
Hysteresis VOUT rising STRICT = 0b 3.8% 4.1% 4.4%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of DCDC4 and after DCDC4 register write (register 0x19) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
IINRUSH Inrush current VIN_DCDC4 = 3.3 V ≤ VINDCDC4 ≤ 5.5 V; 40 µF ≤ COUT ≤ 100 µF 500 mA
RDIS Discharge resistor 150 250 350 Ω
L Nominal inductor value See Table 6-2 1.2 1.5 2.2 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 40 80 100 µF
DCDC5, DCDC6 POWER PATH
VCC DCDC5, 6 input voltage range VIN_BU = 0 V 2.2 3.3 V
VIN_BU DCDC5, 6 input voltage range(1) 2.2 5.5 V
tRISE VCC, VIN_BU rise time VCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V 30 µs
RDS(ON) Power path switch impedance CC to SYS_BU
VCC = 2.4 V, VIN_BU = 0 V 		14.5 Ω
Power path switch impedance IN_BU to SYS_BU
VIN_BU = 3.6 V 		10.5
ILEAK Forward leakage current Into CC pin;
VCC = 3.3 V, VIN_BU = 0 V;
OFF state; FSEAL = 0b;
over full temperature range 		50 300 nA
Reverse leakage current Out of CC pin;
VCC = 1.5 V; VIN_BU = 5.5 V;
over full temperature range 		500
RCC Acceptable CC source impedance IOUT, DCDC5 < 10 µA;
IOUT, DCDC6 < 10 µA 		1000 Ω
IQ Quiescent current Average current into CC pin; RECOVERY or OFF state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and DCDC6 enabled, no load TJ = 25°C 350 nA
QINRUSH Inrush charge VIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF; SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 Ω CCC = 4.7 µF 720 nC
DCDC5 and DCDC6 band-gap sampling period TJ = 25°C 400 ms
DCDC5 (1-V BATTERY BACKUP SUPPLY)
VDCDC5 Output voltage 1 V
DC accuracy 2.7 V ≤ VIN_BU ≤ 5.5 V;
1.5 µA ≤ IOUT ≤ 25 mA
–40°C ≤ TA < 0°C 		–2.5% 2.5%
2.7 V ≤ VIN_BU ≤ 5.5 V
1.5 µA ≤ IOUT ≤ 25 mA
0°C ≤ TA < 105°C 		–2% 2%
2.2 V ≤ VCC ≤ 3.3 V; VIN_BU = 0;
1.5 µA ≤ IOUT ≤ 100 µA 		–2.5% 2.5%
Output voltage ripple L = 10 µH; COUT = 22 µF; 100-µA load, occurs during band-gap sampling 32(9) mVpp
IOUT Continuous output current 2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V 		10 100 µA
2.7 V ≤ VIN_BU ≤ 5.5 V 25 mA
RDS(ON) High-side FET on resistance VIN_BU = 2.8 V 2.5 3.5 Ω
Low-side FET on resistance VIN_BU = 2.8 V 2 3
ILIMIT High-side current limit VIN_BU = 2.8 V 50 mA
VPG Power-good threshold VOUT falling 79% 85% 91%
Hysteresis VOUT rising 6%
L Nominal inductor value Chip inductor, see Table 6-2 4.7 10 22 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 20(10) 47 µF
Tolerance –20% 20%
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
VDCDC6 Output voltage 1.8 V
VDCDC6 DC accuracy 2.7 V ≤ VIN_BU ≤ 5.5 V;
1 µA ≤ IOUT ≤ 25 mA 		–2% 2%
2.2 V ≤ VCC ≤ 3.3 V, VIN_BU = 0;
1 µA ≤ IOUT ≤ 100 µA		 –2% 2%
VDCDC6 Output voltage ripple L = 10 µH; COUT = 22 µF; 100-µA load 30(9) mVpp
IOUT Continuous output current 2.2 V ≤ VCC ≤ 3.3 V
VIN_BU = 0 V 		10 100 µA
2.7 V ≤ VIN_BU ≤ 5.5 V 25 mA
RDS(ON) High-side FET on resistance VIN_BU = 3 V 2.5 3.5 Ω
Low-side FET on resistance VIN_BU = 3 V 2 3
ILIMIT High-side current limit VIN_BU = 3 V 50 mA
VPG Power-good threshold VOUT falling 87% 91% 95%
Hysteresis VOUT rising 3%
L Nominal inductor value Chip inductor, see Table 6-2 4.7 10 22 µH
Tolerance –30% 30%
COUT Output capacitance value Ceramic, X5R or X7R, see Table 6-3 20(10) 47 µF
Tolerance –20% 20%
LDO1 (1.8-V LDO)
VIN_LDO1 Input voltage range VIN_BIAS > VUVLO 1.8 5.5 V
IQ Quiescent current No load 35 µA
VOUT Output voltage range Adjustable through I2C 0.9 3.4 V
DC accuracy VOUT + 0.2 V ≤ VIN ≤ 5.5 V; 0 A ≤ IOUT ≤ 200 mA –2% 2%
IOUT Output current range VIN_LDO1 – VDO = VOUT 0 200 mA
VIN_LDO1 > 2.7 V, VOUT = 1.8 V 0 400
ILIMIT Short circuit current limit Output shorted to GND 445 550 mA
VDO Dropout voltage IOUT = 100 mA, VIN = 3.6 V 200 mV
VPG Power-good threshold VOUT falling STRICT = 0b 86% 90% 94%
STRICT = 1b 95% 95.5% 96%
Hysteresis, VOUT rising STRICT = 0b 3% 4% 5%
STRICT = 1b 0.25%
Deglitch VOUT falling STRICT = 0b 1 ms
STRICT = 1b 50 µs
VOUT rising STRICT = 0b 10 µs
STRICT = 1b 10 µs
Time-out Occurs at enable of LDO and after LDO register write (register 0x1B) 5 ms
VOV Overvoltage detection threshold VOUT rising, STRICT = 1b 104% 104.5% 105%
Hysteresis VOUT falling, STRICT = 1b 0.25%
Deglitch VOUT rising, STRICT = 1b 50 µs
VOUT falling, STRICT = 1b 1 ms
RDIS Discharge resistor 150 250 380 Ω
COUT Output capacitance value Ceramic, X5R or X7R 22 100 µF
LOAD SWITCH 1 (LS1)
VIN_LS1 Input voltage range VIN_BIAS > VUVLO 1.2 3.6 V
RDS(ON) Static on resistance VIN_LS1 = 3.3 V, IOUT = 300 mA, over full temperature range 110 mΩ
VIN_LS1 = 1.8 V, IOUT = 300 mA,
DDR2, LPDDR, MDDR at 266 MHz over full temperature range 		110
VIN_LS1 = 1.5 V, IOUT = 300 mA,
DDR3 at 333 MHz over full temperature range 		110
VIN_LS1 = 1.35 V, IOUT = 300 mA,
DDR3L at 333 MHz over full temperature range 		110
VIN_LS1 = 1.2 V, IOUT = 200 mA,
LPDDR2 at 333 MHz over full temperature range 		150
ILIMIT Short circuit current limit Output shorted to GND 350 mA
tBLANK Interrupt blanking time Output shorted to GND until interrupt is triggered 15 ms
RDIS Internal discharge resistor at output(2) LS1DCHRG = 1 150 250 380 Ω
TOTS Overtemperature shutdown(3) 125 132 139 °C
Hysteresis 10
COUT Nominal output capacitance value Ceramic, X5R or X7R, see Table 6-3 10 100 µF
LOAD SWITCH 2 (LS2)
VIN_LS2 Input voltage range VIN_BIAS > VUVLO 3 5.5 V
VUVLO Undervoltage lockout Measured at IN_LS2. Supply falling(4) 2.48 2.6 2.7 V
Hysteresis Input voltage rising 170 mV
RDS(ON) Static on resistance VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature range 500 mΩ
ILIMIT Short circuit current limit Output shorted to GND; VIN_LS2 ≥ 4 V LS2ILIM[1:0] = 00b 94 126 mA
LS2ILIM[1:0] = 01b 188 251
LS2ILIM[1:0] = 10b 465 631
LS2ILIM[1:0] = 11b 922 1290
ILEAK Reverse leakage current VLS2 > VIN_LS2 + 1 V 12 30 µA
tBLANK Interrupt blanking time Output shorted to GND until interrupt is triggered 15 ms
RDIS Internal discharge resistor at output(2) LS2DCHRG = 1b 150 250 380 Ω
TOTS Overtemperature shutdown(4) 125 132 139 °C
Hysteresis 10
COUT Nominal output capacitance value Ceramic, X5R or X7R, see Table 6-3 1 100 µF
LOAD SWITCH 3 (LS3)
VIN_LS3 Input voltage range VIN_BIAS > VUVLO 1.8 10 V
RDS(ON) Static on resistance VIN_LS3 = 9 V, IOUT= 500 mA, over full temperature range 440 mΩ
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature range 526
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature range 656
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature range 910
ILIMIT Short circuit current limit VIN_LS3 > 2.3 V,
Output shorted to GND		 LS3ILIM[1:0] = 00b 98 126 mA
LS3ILIM[1:0] = 01b 194 253
LS3ILIM[1:0] = 10b 475 738
LS3ILIM[1:0] = 11b 900 1234
VIN_LS3 ≤ 2.3 V,
Output shorted to GND 		LS3ILIM[1:0] = 00b 98 126
LS3ILIM[1:0] = 01b 194 253
LS3ILIM[1:0] = 10b 475 738
tBLANK Interrupt blanking time Output shorted to GND until interrupt is triggered 15 ms
RDIS Internal discharge resistor at output(2) LS3DCHRG = 1 650 1000 1500 Ω
TOTS Overtemperature shutdown(4) 125 132 139 °C
Hysteresis 10 °C
COUT Nominal output capacitance value Ceramic, X5R or X7R, see Table 6-3 1 100 220 µF
BACKUP BATTERY MONITOR
VTH Comparator threshold Ideal level 3 V
Good level 2.6 V
Low level 2.3 V
Accuracy –3% 3%
RLOAD Load impedance Applied from CC to GND during comparison 70 100 130 kΩ
tDLY Measurement delay RLOAD is connected during delay time. Measurement is taken at the end of delay. 600 ms
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLY PGOOD delay time PGDLY[1:0] = 00b 10 ms
PGDLY[1:0] = 01b 20
PGDLY[1:0] = 10b 50
PGDLY[1:0] = 11b 150
tDG Deglitch time PB input Rising edge 100 ms
Falling edge 50 ms
AC_DET input Rising edge 100 µs
Falling edge 10 ms
PWR_EN input Rising edge 10 ms
Falling edge 100 µs
GPIO1 Rising edge 1 ms
Falling edge 1 ms
GPIO3 Rising edge 5 µs
Falling edge 5 µs
tRESET Reset time PB input held low TRST = 0b 8 s
TRST = 1b 15
VIH High level input voltage SCL, SDA, GPIO1, GPIO3 1.3 V
AC_DET, PB 0.66 × IN_BIAS
PWR_EN 1.3
VIL Low level input voltage SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, GPIO3 0 0.4 V
VOH High level output voltage GPO2; ISOURCE = 5 mA; GPO2_BUF = 1 VIN_LS1 – 0.3 VIN_LS1 V
PGOOD_BU; ISOURCE = 100 µA VDCDC6 – 10 mV
VOL Low level output voltage nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2, GPIO3; ISINK = 2 mA 0 0.3 V
nPFO; ISINK = 2 mA 0 0.35
PGOOD_BU; ISINK = 100 µA 0 0.3
VPFI Power-fail comparator threshold Input falling 800 mV
Hysteresis Input rising 40 mV
Accuracy –4% 4%
Deglitch Input falling 25 µs
Input rising 10 ms
IDC34_SEL DC34_SEL bias current Enabled only at power-up 9.05 10 11.93 µA
VDC34_SEL DCDC3 / DCDC4 power-up default selection thresholds Threshold 1 100 mV
Threshold 2 163
Threshold 3 275
Threshold 4 400
Threshold 5 575
Threshold 6 825
Threshold 7 1200
RDC34_SEL DCDC3 / DCDC4 power-up default selection resistor values Setting 0 0 0 7.7 kΩ
Setting 1 11.8 12.1 12.4
Setting 2 19.5 20 20.5
Setting 3 30.9 31.6 32.3
Setting 4 44.4 45.3 46.3
Setting 5 64.8 66.1 67.3
Setting 6 93.6 95.3 97.2
Setting 7 146 150
IBIAS Input bias current SCL, SDA, GPIO1(5), GPIO3(5); VIN = 3.3 V 0.01 1 µA
PB, AC_DET, PFI; VIN = 3.3 V 500 nA
ILEAK Pin leakage current nINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1(6), GPO2(7), GPIO3(6)
VOUT = 3.3 V 		500 nA
OSCILLATOR
ƒOSC Oscillator frequency 2400 kHz
Frequency accuracy TJ = –40°C to +105°C –12% 12%
OVERTEMPERATURE SHUTDOWN
TOTS Overtemperature shutdown Increasing junction temperature 135 145 155 °C
Hysteresis Decreasing junction temperature 20
TWARN High-temperature warning Increasing junction temperature 90 100 110 °C
Hysteresis Decreasing junction temperature 15
(1) IN_BU has priority over CC input.
(2) Discharge function disabled by default.
(3) Switch is temporarily turned OFF if temperature exceeds OTS threshold.
(4) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
(5) Configured as input.
(6) Configured as output.
(7) Configured as open-drain output.
(8) 500-µF of remote capacitance can be supported for DCDC1/2.
(9) For PHP package: 160mVpp at -40°C, and 120mVpp from 25°C to 105°C.
(10) For PHP package: 40µF.