SBVS054K November   2004  – June 2025 TPS730

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Foldback Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Operation
      2. 7.1.2 Capacitor Recommendations
      3. 7.1.3 Input and Output Capacitor Requirements
      4. 7.1.4 Noise-Reduction and Feed-Forward Capacitor Requirements
      5. 7.1.5 Reverse Current Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.5.1.2 Thermal Considerations
        3. 7.5.1.3 Power Dissipation
      2. 7.5.2 Layout Examples
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TPS730YZQ Nanostar™ Wafer Chip Scale Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from Revision J (April 2015) to Revision K (June 2025)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Added new silicon (M3) devices to documentGo
  • Changed entire document to identify the features and differences of the legacy chip and new chip and the adjustable and fixed versions of the deviceGo
  • Changed Features, Applications, and Description sectionsGo
  • Changed front-page figure Go
  • Changed Pin Configuration and Functions section: Changed DBV pinout NR pins to NC/NR, added NC/NR pin row with reference to TPS7A20 for lower noise performance to Pin Functions tableGo
  • Added new silicon curves to Typical Characteristics sectionGo
  • Deleted (170 µA, typically) from quiescent current discussion in Overview sectionGo
  • Changed Functional Block Diagrams sectionGo
  • Changed Shutdown sectionGo
  • Changed Foldback Current Limit sectionGo
  • Changed Input and Output Capacitor Requirements sectionGo
  • Changed Reverse Current Operation sectionGo
  • Changed input capacitor value from 0.1µF to 1µF in Detailed Design Procedure sectionGo
  • Changed Application Curves sectionGo
  • Added new figures to Layout Examples sectionGo
  • Added M3 information to Ordering Information tableGo

Changes from Revision I (February 2011) to Revision J (April 2015)

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Changed fourth bullet of Features list to low noise Go
  • Changed front-page figure Go
  • Added Pin Configuration and Functions sectionGo
  • Added condition statement to Typical Characteristics Go
  • Moved Ordering Information to Device Nomenclature section Go