SBVS054K November   2004  – June 2025 TPS730

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Foldback Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Operation
      2. 7.1.2 Capacitor Recommendations
      3. 7.1.3 Input and Output Capacitor Requirements
      4. 7.1.4 Noise-Reduction and Feed-Forward Capacitor Requirements
      5. 7.1.5 Reverse Current Operation
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.5.1.2 Thermal Considerations
        3. 7.5.1.3 Power Dissipation
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 TPS730YZQ Nanostar™ Wafer Chip Scale Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over recommended operating temperature range, TJ = –40°C to +125°C VEN = VIN, VIN = VOUT(nom) + 1V, IOUT = 1mA, COUT = 10µF, CNR = 0.01µF (unless otherwise noted). All typical values at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range (1) 2.7 5.5 V
IOUT Continuous output current 0 200 mA
VFB Internal reference (TPS73001) 1.201 1.225 1.25 V
VOUT Output voltage range (TPS73001) VFB 5.5 – VDROPOUT V
Output voltage accuracy 0µA < IOUT < 200mA, VOUT+ 1V < VIN < 5.5V -2% VOUT(nom) 2%
ΔVOUT/ΔVIN Line regulation (1) VOUT + 1V ≤ VIN ≤ 5.5V 0.05 %/V
ΔVOUT/ΔIOUT Load regulation 0µA ≤ IOUT ≤ 200mA 5 mV
VDO(2) Dropout voltage  VIN= VOUT - 0.1V, IOUT = 200mA  120 210 mV
ICL Output current limit VOUT = 0V(Legacy chip) 285 600 mA
VIN = VOUT(NOM) + 1 V, VOUT = 0.9 x VOUT(NOM) (new chip only) 320 460
ISC Short-circuit current limit VOUT = 0V (New Chip) 175 mA
IGND Quiescent current (GND current) 0µA ≤ IO ≤ 200mA (Legacy Chip) 170 220 µA
0µA ≤ IO ≤ 200mA(New Chip) 250 1000
ISHDN Shutdown current VEN = 0V, 2.7V < VI < 5.5V (legacy chip)(3) 0.07 1 µA
VEN = 0V, 2.7V < VI < 5.5V (new chip)(3) 0.01 1
IFB Feedback pin current  VFB = 1.8V (legacy chip) 1 µA
VFB = 1.8V (new chip) 0.05
PSRR Power-supply rejection ratio  f = 100Hz IOUT = 10mA (legacy chip) 70 dB
IOUT = 10mA (new chip) 64
IOUT = 200mA (legacy chip) 68
IOUT = 200mA (new chip) 65
f = 10kHz IOUT = 200mA (legacy chip) 70
IOUT = 200mA (new chip) 49
f = 100kHz IOUT = 200mA (legacy chip) 43
IOUT = 200mA (new chip) 39
Vn Output noise voltage  BW = 200Hz to 100kHz, IOUT = 200mA CNR = 0.01µF 33 µVRMS
BW = 200Hz to 100kHz, IOUT = 200mA (new chip)(4) 69
tSTR Time, start-up  RL = 14 Ω, COUT = 1µF CNR = 0.001µF 50 µs
CNR = 0.0047µF 50
CNR = 0.01µF 50
(new chip)(4) 500
VEN(HI) High-level enable input voltage 2.7V ≤ VIN ≤ 5.5V  1.7 VIN V
2.7V ≤ VIN ≤ 5.5V (new chip) 0.85 VIN
VEN(LOW) Low-level enable input voltage 2.7V ≤ VIN ≤ 5.5V 0 0.7 V
2.7V ≤ VIN ≤ 5.5V (new chip) 0 0.425
IEN Enable pin current VEN = 0 V –1 1 µA
VUVLO UVLO threshold VIN rising (legacy chip) 2.25 2.65 V
VIN rising (new chip) 1.32 1.6
VUVLO(HYST) UVLO hysteresis VCC rising (legacy chip) 100 mV
VCC rising (new chip) 130
(1) Minimum VIN is 2.7 V or VOUT + VDO, whichever is greater.
(2) Dropout is not measured for the TPS73018 and TPS73025 because minimum VIN = 2.7V.
(3) For adjustable versions, this parameters applies only after VIN is applied; then VEN transitions high to low.
(4) New Chip does not have a Noise Reduction pin.