SLVS337E March   2001  – January 2025 TPS792

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout (UVLO)
      2. 6.3.2 Shutdown
      3. 6.3.3 Active Discharge (New Chip)
      4. 6.3.4 Foldback Current Limit
      5. 6.3.5 Thermal Protection
      6. 6.3.6 Reverse Current
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Operation
      2. 7.1.2 Exiting Dropout
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Capacitor Recommendations
        2. 7.2.2.2 Input and Output Capacitor Requirements
        3. 7.2.2.3 Noise Reduction and Feed-Forward Capacitor Requirements
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
        2. 7.4.1.2 Power Dissipation and Junction Temperature
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Modules
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

over recommended operating temperature range, TJ = –40°C to +125°C VEN = VIN, VIN = VO(typ) + 1V, IOUT = 1 mA, COUT = 10 µF, CNR = 0.01 µF (Legacy Chip) (unless otherwise noted). All typical values at TJ= 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOUT Output accuracy TPS79201 (1) 0µA < IOUT < 100mA 1.22V < VOUT < 5.2V 0.98 VOUT VOUT 1.02 VOUT V
TPS79225 (Legacy chip only) 0µA < IOUT < 100mA 1.22V < VOUT < 5.2V 2.45 2.5 2.55 V
TPS79228 (Legacy chip only) 0µA < IOUT < 100mA 1.22V < VOUT < 5.2V 2.744 2.8 2.856 V
TPS79230 0µA < IOUT < 100mA, 4V < VIN < 5.5V 2.94 3 3.06
IGND Quiescent current (GND current) 0µA ≤ IO ≤ 100mA (Legacy Chip) 170 250 µA
0µA ≤ IO ≤ 100mA(New Chip) 250 1000
ΔVOUT/ΔIOUT Load regulation(2) 0µA ≤ IOUT ≤ 100mA 5 mV
ΔVOUT/ΔVIN Line regulation VOUT + 1V ≤ VIN ≤ 5.5V 0.05 0.12 %/V
Vn Output noise voltage (TPS7928) (Legacy chip only) BW = 100Hz to 100kHz, IOUT = 100mA CNR = 0.001µF 50 µVRMS
BW = 100Hz to 100kHz, IOUT = 100mA CNR = 0.0047µF 33
BW = 100Hz to 100kHz, IOUT = 100mA CNR = 0.01µF 31
BW = 100Hz to 100kHz, IOUT = 100mA CNR = 0.1µF 27
Output noise voltage (TPS79230) BW = 100Hz to 100kHz, IOUT = 100mA (New Chip) 69
tSTR Time, start-up (TPS79230) RL = 14 Ω, COUT = 1µF CNR = 0.001µF 50 µs
CNR = 0.0047µF 70
CNR = 0.01µF 90
(New Chip) 500
ICL Output current limit VOUT = 0V(Legacy Chip) 285 600 mA
ICL Output current limit VIN = VOUT(NOM) + 1 V, VOUT = 0.9 x VOUT(NOM) (New Chip only) 320 460 mA
ISC Short-circuit current limit VOUT = 0V (New Chip) 175 mA
ISHDN Shutdown current VEN = 0V, 2.7V < VI < 5.5V(Legacy Chip) 0.07 1 µA
VEN = 0V, 2.7V < VI < 5.5V(New Chip) 0.01 1
VEN(HI) High-level enable input voltage 2.7V ≤ VIN ≤ 5.5V  1.7 VIN V
VEN(HI) High-level enable input voltage 2.7V ≤ VIN ≤ 5.5V (New Chip) 0.85 VIN V
VEN(LOW) Low-level enable input voltage 2.7V ≤ VIN ≤ 5.5V 0 0.7 V
VEN(LOW) Low-level enable input voltage 2.7V ≤ VIN ≤ 5.5V (New Chip) 0 0.425 V
IEN Enable pin current VEN = 0 V –1 1 µA
VREF Internal reference (TPS79201) 1.201 1.225 1.25 V
PSRR Power-supply rejection ratio (TPS79228) f = 100Hz IOUT = 10mA (Legacy Chip) 70 dB
Power-supply rejection ratio (TPS79230) IOUT = 10mA (New Chip) 64
Power-supply rejection ratio (TPS79228) IOUT = 100mA (Legacy Chip) 72
Power-supply rejection ratio (TPS79230) IOUT = 100mA (New Chip) 64
Power-supply rejection ratio (TPS79228) f = 10kHz IOUT = 100mA (Legacy Chip) 75
Power-supply rejection ratio (TPS79230) IOUT = 100mA (New Chip) 49
Power-supply rejection ratio (TPS79228) f = 100kHz IOUT = 100mA (Legacy Chip) 47
Power-supply rejection ratio (TPS79230) IOUT = 100mA (New Chip) 39
VDO (3) Dropout voltage (TPS79228) VIN= VOUT - 0.1V, IOUT = 100mA (Legacy Chip only) 60 110 mV
Dropout voltage (TPS79230) VIN= VOUT - 0.1V, IOUT = 100mA 55 100
VUVLO UVLO threshold VIN rising (Legacy Chip) 2.25 2.65 V
VIN rising (New Chip) 1.32 1.6
VUVLO(HYST) UVLO hysteresis TJ = 25°C, VCC rising (Legacy Chip) 100 mV
TJ = 25°C, VCC rising (New Chip) 130
(1) The minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. The maximum IN voltage is 5.5 V. The maximum output current is 100 mA.
(2) If VOUT ≤ 2.5V then VIN(min) = 2.7V, VIN(max) = 5.5V: Line regulation(mV) = (%/V) * VOUT (VIN(max) - 2.7V) / 100 *100
(3) IN voltage equals VOUT(nom) – 100 mV; The TPS79225 dropout voltage is limited by the input voltage range limitations.