SBVS370F May   2019  – September 2025 TPS7B81-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Device Enable (EN)
      2. 6.3.2 Undervoltage Shutdown
      3. 6.3.3 Current Limit
      4. 6.3.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operation With VIN Lower Than 3V
      2. 6.4.2 Operation With VIN Larger Than 3V
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Dissipation
        1. 7.1.1.1 Estimating Junction Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.1 Power Dissipation

Circuit reliability demands that proper consideration is given to device power dissipation, location of the circuit on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator must be as free as possible of other heat-generating devices that cause added thermal stresses.

As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage difference and load conditions. PD can be approximated using Equation 1:

Equation 1. P D = V O U T - V I N × I O U T

An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low dropout of the device allows for maximum efficiency across a wide range of output voltages.

The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that conduct heat to any inner plane areas or to a bottom-side copper plane.

The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device. Power dissipation and junction temperature are most often related by the junction-to-ambient thermal resistance (RθJA) of the combined PCB, device package, and the temperature of the ambient air (TA), according to Equation 2. The equation is rearranged for output current in Equation 3.

Equation 2. T J = T A + R θ J A × P D
Equation 3. I O U T = T J - T A ÷ R θ J A × V I N - V O U T

Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the planes. The RθJA recorded in the v table is determined by the JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal performance. Note that for a well-designed thermal layout, RθJA is actually the sum of the package junction-to-case (bottom) thermal resistance (RθJCbot) plus the thermal resistance contribution by the PCB copper.

Figure 7-1 through Figure 7-6 show the functions of RθJA and ψJB vs copper area and thickness. These plots are generated with a 101.6mm x 101.6mm x 1.6mm PCB of two and four layers. For the four layer board, inner planes use 1oz copper thickness. Outer layers are simulated with both 1oz and 2oz copper thickness. A 2x 1 array of thermal vias of 300µm drill diameter and 25µm Cu plating is located beneath the thermal pad of the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. Each of the layers has a copper plane of equal area.

TPS7B81-Q1 RθJA versus Cu Area for the WSON (DRV) PackageFigure 7-1 RθJA versus Cu Area for the WSON (DRV) Package
TPS7B81-Q1 ψJB versus Cu Area for the WSON (DRV) PackageFigure 7-2 ψJB versus Cu Area for the WSON (DRV) Package
TPS7B81-Q1 RθJA versus Cu Area for the HVSSOP (DGN) PackageFigure 7-3 RθJA versus Cu Area for the HVSSOP (DGN) Package
TPS7B81-Q1 ψJB versus Cu Area for the HVSSOP (DGN) PackageFigure 7-4 ψJB versus Cu Area for the HVSSOP (DGN) Package
TPS7B81-Q1 RθJA versus Cu Area for the TO-252 (KVU) PackageFigure 7-5 RθJA versus Cu Area for the TO-252 (KVU) Package
TPS7B81-Q1 ψJB versus Cu Area for the TO-252 (KVU) PackageFigure 7-6 ψJB versus Cu Area for the TO-252 (KVU) Package