SLVSFL2A May 2021 – August 2021 TPS7H4002-SP
The switching frequency of the device supports three modes of operations. The modes of operation are set by the conditions on the RT and SYNC pins. At a high level, these modes can be described as primary-secondary, internal oscillator, and external synchronization modes.
In primary-secondary mode, the RT pin of the primary device should be left floating; the internal oscillator is set to 500 kHz, and the SYNC pin is set as an output clock. The SYNC output is in phase with respect to the internal oscillator of the primary device. SYNC out signal level is the same as VIN level with 50% duty cycle. SYNC signal feeding the secondary module, which is in phase with the primary clock, gets internally inverted (180° out of phase with the primary clock) internally in the secondary module. When trying to parallel with another converter, the RT pin of the second (secondary) converter must have its RT pin populated such that the converter frequency of the secondary converter must be within ±5% of the primary converter. This is required because the RT pin also sets the proper operation of slope compensation.
In internal oscillator mode, a resistor is connected between the RT pin and GND. The SYNC pin requires a 10-kΩ resistor to GND for this mode to be effective. The switching frequency of the device is adjustable from 100 kHz to 1 MHz by placing a maximum of 510 kΩ and a minimum of 47 kΩ respectively. To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 7-4. To reduce the solution size, the designer should set switching frequency as high as possible, but consider the tradeoffs of supply efficiency and minimum controllable on-time.
In external synchronization mode, a resistor is connected between the RT pin and GND. The SYNC pin requires a toggling signal for this mode to be effective. The switching frequency of the device goes 1:1 with that of SYNC pin. External system clock-user supplied sync clock signal determines the switching frequency. If no external clock signal is detected for 20 µs, then TPS7H4002-SP transitions to its internal clock, which is typically 500 kHz. An external synchronization using an inverter to obtain phase inversion is necessary. RT values of the primary and secondary converter must be within ±5% of the external synchronization frequency. This is necessary for proper slope compensation. A resistance in the RT pin is required for proper operation of the slope compensation circuit. To determine the RT resistance for a given switching frequency, use Equation 4 or the curve in Figure 7-4.
These modes are described in Table 7-1.
|RT PIN||SYNC PIN||SWITCHING FREQUENCY||DESCRIPTION AND NOTES|
|Float||Generates an output signal||500 kHz||SYNC pin behaves as an output. SYNC output signal is in phase with the internal 500-kHz switching frequency.|
|47-kΩ to 510-kΩ resistor to AGND||10-kΩ resistor to GND||100 kHz to 1 MHz||Internally generated switching frequency is based upon the resistor value present at the RT pin.|
|User-supplied sync clock or |
TPS7H4002-SP primary device sync output
|Internally synchronized to external clock. External clock is inverted internally.||Set value of RT that corresponds to the externally supplied sync frequency.|