SLUSCX8C March 2019 – March 2021 TPS92682-Q1
PRODUCTION DATA
LHIFT register determines the maximum count value of a 6-bit counter used for the ILIM Fault Timer. The clock for the ILIM Fault Timer is the CHxCLK. The settings in this register are applied when LH pin is set high.
ADDR | REGISTER | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | DEFAULT |
---|---|---|---|---|---|---|---|---|---|---|
1Fh | LHIFT | RSVD | RSVD | RSVD | RSVD | LHCH2IFT1:0 | LHCH1IFT1:0 | 00001010 |
00: ILIM Fault Timer maximum count = 4
01: ILIM Fault Timer maximum count = 8
10: ILIM Fault Timer maximum count = 16
11: ILIM Fault Timer maximum count = 32
If 2PH is set to '1', only CH1 parameters are used and only ILIM Fault Timer 1 is active. In this case, ILIM Fault Timer-1 affects both channels.