SLUSCX8 Data sheet

SLUSCX8C March 2019 – March 2021 TPS92682-Q1

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

DAP|32
- MPDS380A
RHB|32
- MPQF130D
RHM|32
- MPQF152B

Thermal pad, mechanical data (Package|Pins)

DAP|32
- PPTD363
RHB|32
- QFND644
RHM|32
- QFND588

Orderable Information

6.5 Electrical Characteristics

–40°C < T_J < 150°C, V_IN= 14V, VIADJDACx = 0xDF, C_VCC = 1μF, C_VDD = 1μF, C_COMP = 2.2nF, R_CS = 100mΩ, R_T = 50kΩ, V_PWM = 5V, no load on GATE and PDRV, DIV=4 (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT VOLTAGE (VIN)
I_IN-SHDN	Input shutdown current	V_EN = 0 V, V_CSP = V_CSN = V_PDRV = 0 V		10		µA
I_IN-SHDN	Input shutdown current	V_EN = 0 V, V_CSP = 14 V		10.5		µA
I_IN-STBY	Input standby current	Software EN1 and EN2 = 0, V_PWM1 = V_PWM2 = 0 V		2.3		mA
I_IN-SW	Supply switching current	VCC=7.5V, C_GATEx = 1nF, Both channels are switching		10		mA
VCC BIAS SUPPLY
VCC_UVLO	Supply under-voltage protection	VCC rising threshold, V_VIN = 8 V		4.5	4.9	V
		VCC falling threshold, V_VIN = 8 V	3.7	4.1		V
		Hysteresis		411		mV
VCC_(REG)	VCC regulation voltage	No load	7	7.5	8	V
I_VCC(LIMIT)	VCC current limit	V_VCC = 0 V	40			mA
VCC_DO	VCC LDO dropout voltage	I_VCC = 30 mA, V_VIN = 4.5 V		300	475	mV
VDD BIAS SUPPLY
VDD_(REG)	VDD regulation voltage	No load	4.85	5	5.25	V
VDD_(POR-RISE)	VDD rising threshold	V_VIN = 5 V			4.1	V
VDD_(POR-FALL)	VDD falling threshold	V_VIN = 5 V	2.58			V
VDD_DO	VDD LDO dropout voltage	I_VDD = 15 mA, V_VIN = 4.5 V			400	mV
I_VDD(LIMIT)	VDD current limit	V_VDD = 0 V	30	39	50	mA
ENABLE INPUT
V_EN	EN voltage threshold		1.12	1.21	1.3	V
V_EN-HYS	EN pin hysteresis	Difference between rising and falling threshold		100		mV
I_EN	EN PIN input bias current	V_EN = 14 V		5		µA
OSCILLATOR
f_SW	Switching frequency	RT = 200kΩ, DIV=4	85	100	115	kHz
f_SW	Switching frequency	RT = 50kΩ, DIV=4	340	400	460	kHz
V_RT	RT PIN voltage			1		V
SPREAD SPECTRUM DAC
DAC_DT-BITs	Internal DAC resolution			8		Bits
DAC_DT-MAX	DAC maximum voltage			1.156		V
DAC_DT-MIN	DAC minimum voltage			855		mV
GATE DRIVER
R_GH	Driver pull-up resistance	I_GATE = –10 mA		5.1	11.2	Ω
R_GL	Driver pull-down resistance	I_GATE = 10 mA		4.1	10.5	Ω
SWITCH CURRENT SENSE and ILIMIT
V_ILIM(THR)	ILIM threshold PWM = LOW	V_PWMx= 0 V, CHxILIM = XX	649	711	769	mV
	ILIM threshold PWM = HIGH	V_PWMx= 5 V, CHxILIM = 11	228	253	277	mV
		V_PWMx= 5 V, CHxILIM = 10	132	151	171	mV
		V_PWMx= 5 V, CHxILIM = 01	82	100.6	119	mV
		V_PWMx= 5 V, CHxILIM = 00	57	75.2	93	mV
t_IS(BLANK)	Leading edge blanking	CHxLEB = 0		75		ns
t_IS(BLANK)	Leading edge blanking	CHxLEB = 1		150		ns
t_{ILIMIT(DELAY)}	ISx to GATEx delay			86		ns
PWM COMPARATOR
D_MAX	Maximum duty cycle			90		%
V_LVx-Delta	Difference between CH1 and CH2 PWM comparator offset		–17.5		17.5	mV
I_LVx	IS level shift bias current	No slope compensation added		40		µA
T_PWM-Delta	Turn-off propagation delay from input of PWM comp. to gate output			100		ns
T_PWMDEL-Delta	Difference between CH1 and CH2 PWM comp. propagation delay		–30		30	ns
CURRENT SENSE AMPLIFIER (CSP, CSN)
V_(CSP-CSN)x	Current Sense REG Voltage	V_CSP(CM) = 14 V, IADJDAC = 0×FF	165.8	172.7	179.6	mV
		V_CSP(CM) = 14V, IADJDAC = 0x95	96.5	100.8	104.5	mV
		V_CSP(CM) = 14V, IADJDAC = 0×0F		10.3		mV
CS_(BW)	Current sense unity gain bandwidth			500		kHz
G_CS	Current Sense Gain = V_IADJ/V_(CSP-CSN)	V_CS = 150 mV, V_CSP = 60 V		14		V/V
K_(OCP)	Ratio of over-current detection threshold to V_IADJ	K_(OCP) = V_(OCP-THR)/V_IADJ	1.41	1.53	1.66	V/V
K_(UC)	Ratio of under-current detection threshold to V_IADJ	K_(UC) = V_(UC-THR)/V_IADJ		0.5		V/V
I_CSP(BIAS)	CSP bias current	V_CSP = V_CSN = V_PDRV = 14 V		59		µA
I_CSN(BIAS)	CSN bias current	V_CSP = V_CSN = V_PDRV = 14 V		59		µA
SSDAC
DAC_SS-BITs	Internal DAC resolution			8		Bits
DAC_SS-FS	DAC full scale voltage			2.8		V
CALDAC
DAC_CAL-BITs	Switch current sense calibration DAC			3		Bits
DAC_CAL-RES	Offset-per-Bit applied to the switch current sense			2.5		mV
FAULT FLAG ( FLTx)
R_( FLT)	Open-drain pull down resistance			36		Ω
VIADJDAC
DAC_ADJ-BITs	Internal DAC resolution			8		Bits
DAC_ADJ-FS	DAC full scale voltage		2.32	2.4	2.48	V
ERROR AMPLIFIER (COMP)
g_M	Transconductance	HG = 0		122		µA/V
g_M	Transconductance	HG = 1		914		µA/V
I_COMP(SRC)	COMP source current capacity	IADJx = 0×95, V_(CSP-CSN) = 0 V, HG = 0		129		µA
I_COMP(SRC)	COMP source current capacity	IADJx = 0×95, V_(CSP-CSN) = 0 V, HG = 1		777		µA
I_COMP(SINK)	COMP sink current capacity	IADJx = 0×00, V_(CSP-CSN) = 0.1 V, HG = 0		129		µA
I_COMP(SINK)	COMP sink current capacity	IADJx = 0×00, V_(CSP-CSN) = 0.1 V, HG = 1		783		µA
EA_(BW)	Error amplifier bandwidth	Gain = –3 dB, HG = 0		5		MHz
EA_(BW)	Error amplifier bandwidth	Gain = –3 dB, HG = 1		1		MHz
V_COMP(RST)	V_COMP reset voltage			100		mV
R_COMP(DCH)	COMPx discharge FET R_DSON			248		Ω
R_COMP(DIFF)	COMP1 to COMP2 short path resistance			300		Ω
SLOPEDAC
DAC_SLP-FS	DAC full scale voltage			0.36		V
VFB
VFB_ERR	Regulation voltage error		–4		4	%
VFB_BIAS	V_FB pin pull up bias current			200		nA
OVDAC
V_OV(THR)	OV limit threshold, 0%	CHxOVDAC = 000	1.2	1.237	1.27	V
	OV limit threshold, 2.5%	CHxOVDAC = 001		1.268		V
	OV limit threshold, 5%	CHxOVDAC = 010		1.299		V
	OV limit threshold, 7.5%	CHxOVDAC = 011		1.329		V
	OV limit threshold, 10%	CHxOVDAC = 100		1.36		V
	OV limit threshold, 12.5%	CHxOVDAC = 101		1.391		V
	OV limit threshold, 15%	CHxOVDAC = 110		1.422		V
	OV limit threshold, 20%	CHxOVDAC = 111		1.483		V
I_OV-HYS	OV hysteresis current		11.5	20.5	28.5	µA
UV (Output Under Voltage)
V_UV(THR)	Under voltage protection threshold		40	53.2	67	mV
t_UV(BLANK)	Under voltage blanking period			5		µs
DIGITAL INPUTs (PWMx, SYNC, LH, SSN, SCK, MOSI)
I_BIAS	Input bias current	Except PWM inputs			1	µA
VT_INPUT-FALL	Falling threshold		0.7			V
VT_INPUT-RISE	Rising threshold				1.85	V
PWM INPUT (PWM)
R_PWM(PD)	PWM pull-down resistance			10		MΩ
t_DLY(RISE)	PWM rising to PDRV delay	C_PDRV = 1 nF		235		ns
t_DLY(FALL)	PWM falling to PDRV delay	C_PDRV = 1 nF		222		ns
PFET GATE DRIVE
V_PDRV(OFF)	PDRV off-state voltage	V_CSP = 14 V		14		V
V_PDRV(ON)	PDRV on-state voltage	V_CSP = 14 V		7.34		V
I_PDRV(SINK)	PDRV sink current	V_CSP – V_PDRV = 5 V, pulsed < 100 µs		29		mA
R_PDRV	PDRV pull up resistance	V_CSP – V_PDRV = 0 V, pulsed < 100 µs		83.5		Ω
SPI INTERFACE
V_OL-MISO	Output low voltage threshold	I_(MISO) = 10 mA		0.25		V
R_DS-MISO				25		Ω
C_MISO				10		pF
t_SS-SU	SSN setup time	Falling edge of SSN to 1^st SCK rising edge	500			ns
t_SS-H	SSN hold time	Falling edge of 16^th SCK to SSN rising edge	250			ns
t_SS-HI	SSN high time	Time SSN must remain high between transactions	1			µs
t_SCK	SCK period	Clock period	500			ns
D_SCK	SCK duty cycle	Clock duty cycle	40		60	%
t_MOSI-SU	MOSI setup time	MOSI valid to rising edge SCK	125			ns
t_MOSI-H	MOSI hold time	MOSI valid after rising edge SCK	140			ns
t_MISO-HIZ	MISO tristate time	Time to tristate MISO after SSN rising edge	110		320	ns
t_MISO-HL	MISO valid high-to-low	Time to place valid "0" on MISO after falling SCK edge.			320	ns
t_MISO-LH	MISO valid low-to-high	Time to tri-state MISO after falling SCK edge. t_RC is the time added by the application total capacitance and resistance.			320+t_RC	ns
T_ZO-HL	MISO drive time high-to-low	SSN Falling Edge to MISO Falling			320	ns