SLVSDF7A December   2016  – July 2017 TPSM84A21

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Transient Response
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Package Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage (VADJ)
      2. 7.3.2  Input and Output Capacitance
      3. 7.3.3  Transient Response
        1. 7.3.3.1 Transient Response Waveforms
      4. 7.3.4  Oscillator Frequency
      5. 7.3.5  External Clock Syncronization
      6. 7.3.6  Soft Start
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Gate Driver (VG)
      9. 7.3.9  Startup into Pre-biased Outputs
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Output Undervoltage/Overvoltage Protection
      13. 7.3.13 Enable (EN)
      14. 7.3.14 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Input and Output Capacitance
        3. 8.2.2.3 Power Good (PGOOD)
        4. 8.2.2.4 External VG Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over –40°C to +85°C free-air temperature range, VIN = 12 V, VOUT = 1.0 V, IOUT = IOUT max, FSW = 4 MHz,
External CIN = 2 × 22 µF 25 V 1210 ceramic plus 1 × 100 µF electrolytic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT VOLTAGE (VIN)
VIN VIN input voltage range Over VOUT range 8 14 V
VIN_UVLO VIN under voltage lock out VIN increasing 7.65 7.95 V
VIN decreasing 7.4 V
VIN_HYS VIN UVLO hysteresis 250 mV
IVIN_EN VIN standby current EN = 0 V 47 µA
OUTPUT VOLTAGE (VOUT)
VOUT(ADJ) Output voltage adjust range Over IOUT range 0.55 1.35 V
VOUT Set-point voltage tolerance VOUT = 1.0 V, TA = 25°C, IOUT = 0 A -1.0% +1.0%(1)
Temperature variation VOUT = 1.0 V, –40°C ≤ TA ≤ 85°C, IOUT = 0 A ±0.2%(2)
Line regulation VOUT = 1.0 V, over VIN range, IOUT = 0 A, TA = 25°C ±0.03%
Load regulation VOUT = 1.0 V, over IOUT range, TA = 25°C ±0.1%
VOUT Ripple Output Voltage Ripple 20-MHz Bandwidth, peak-to-peak 8 mV
OUTPUT CURRENT
IOUT Output current See SOA graph for derating over temperature. 0 10 A
Overcurrent threshold ILIM = open 15 A
ILIM = 47 kΩ 11.25 A
PERFORMANCE
ƞ Efficiency(2) VIN = 12 V, IOUT = 5 A VOUT = 0.8 V, VG = open 79.8%
VOUT = 0.8 V, VG = 5 V 82.5%
VOUT = 1.0 V, VG = open 82.6%
VOUT = 1.0 V, VG = 5 V 84.9%
VOUT = 1.2 V, VG = open 84.5%
VOUT = 1.2 V, VG = 5 V 86.5%
Transient Response(2) 1 A/µs load step,
25% to 75% IOUT(max), COUT= 0 µF		 VOUT over/undershoot 10 mV
Recovery Time 10 µs
5 A/µs load step,
25% to 75% IOUT(max), COUT= 0 µF		 VOUT over/undershoot 25 mV
Recovery Time 10 µs
SOFT START
TSS Internal soft start time(2) 4.1 ms
INTERNAL REGULATOR (VG)
VVG VG pin output voltage 4.4 4.8 5.0 V
ENABLE AND UNDER-VOLTAGE LOCK-OUT (EN/UVLO)
VEN EN threshold range 1.17 1.23 1.27 V
IEN Input current EN threshold + 50 mV –4 µA
Hysteresis current EN threshold – 50 mV –1 µA
POWER GOOD (PGOOD)
VPGOOD PGOOD Thresholds (2) VVOUT falling (Fault) 89%
VVOUT rising (Good) 95%
VVOUT rising (Fault) 109%
VVOUT falling (Good) 104%
Minimum VIN for valid PGOOD(2) VPGOOD ≤ 0.5 V at 100 µA 1.2 2.75 V
PGOOD Low Voltage IPGOOD = 1.7 mA 0.25 0.3 V
THERMAL SHUTDOWN
Thermal shutdown threshold 135 °C
Thermal shutdown hysteresis 20 °C
CAPACITANCE
CIN External Input Capacitance Ceramic type 0(3) 44 µF
Non-ceramic type 0(3) 100 µF
COUT External Output Capacitance Ceramic type 0(4) 1000(5) µF
Non-ceramic type 0(4) 2200(5) µF
Equivalent series resistance (ESR) 35 mΩ
(1) The stated limit of the set-point tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.
(2) Specified by design. Not production tested.
(3) Internal to the device, 66.1 µF (nominal) ceramic input capacitance is present. This device does not require additional input capacitance. If adding additional input capacitance, locate the capacitors close to the device.
(4) Internal to the device, 185 µF (nominal) ceramic output capacitance is present. This device does not require additional output capacitance to operate. Adding additional output capacitance near the load improves the response of the device to load transients.
(5) The maximum output capacitance listed in the table is the maximum amount that has been tested and validated for proper start-up, stability, and transient response. It may be possible to operate with additional output capacitance, however, additional validation is required.