10.1 Layout Guidelines
To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 20 and Figure 22 show typical, top-side PCB layouts. Some considerations for an optimized layout are:
- Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
- When adding input and output ceramic capacitors, place them close to the device pins to minimize high frequency noise.
- Locate any additional output capacitors between the ceramic capacitors and the load.
- Keep AGND and PGND separate from one another. The connection is made internal to the device.
- Place RSET as close as possible to the VADJ pin.
- Use multiple vias to connect the power planes to internal layers.