SLVSDF7A December   2016  – July 2017 TPSM84A21

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Transient Response
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Package Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage (VADJ)
      2. 7.3.2  Input and Output Capacitance
      3. 7.3.3  Transient Response
        1. 7.3.3.1 Transient Response Waveforms
      4. 7.3.4  Oscillator Frequency
      5. 7.3.5  External Clock Syncronization
      6. 7.3.6  Soft Start
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Gate Driver (VG)
      9. 7.3.9  Startup into Pre-biased Outputs
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Output Undervoltage/Overvoltage Protection
      13. 7.3.13 Enable (EN)
      14. 7.3.14 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Input and Output Capacitance
        3. 8.2.2.3 Power Good (PGOOD)
        4. 8.2.2.4 External VG Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

MOJ Package
20-Pin QFM
Top View
TPSM84A21 EaglesPinout3.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 16 — Zero voltage reference for analog control circuitry. Connect RSET between this pin and VADJ close to the device. Do not connect this pin to PGND; the connection is made internal to the device.
EN/UVLO 2 I Enable and UVLO adjust pin. When this pin voltage is low, the device is disabled. Use an open drain, open collector, or a suitable logic gate device to control the enable function. A resistor divider between this pin, PGND, and VIN adjusts the UVLO voltage.
ILIM 3 I Current limit setting pin. Leave this open for the full current limit threshold of 15 A. Connect a 47 kΩ resistor between this pin and PGND to reduce the current limit threshold to 11.25 A.
PGND 1, 4, 5, 6, 7, 8, 10, 18, 20 — Power ground of the device. Connect these pins to the power ground plane of the PCB. Thermal vias to internal ground planes should be added beneath pin 20.
PGOOD 12 O Power good indicator. This pin is an open-drain output and will assert low if the output voltage is greater than ±5% from the programmed value or due to thermal shutdown, under-voltage, or EN shutdown. A pull-up resistor is required. VG can be used as a PGOOD pull-up source.
VS+ 14 I Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect the pin to VOUT at the load for improved regulation.
SYNC 11 I External clock synchronization pin. An external clock signal can be applied to this pin to synchronize the switching frequency within ±10% of the nominal switching frequency (4 MHz).
VADJ 15 I Output voltage adjust pin. Connecting a resistor between this pin and AGND sets the output voltage.
VG 13 I Gate driver supply pin. If this pin is left open, an internal LDO will generate the gate driver supply voltage from the VIN pin. To reduce power consumption and improve efficiency, power this pin with an external 5-V supply. This pin can be used as a PGOOD pull-up source.
VIN 17, 19 I Input Voltage. These pins supply all of the power to the converter. Connect VIN to a supply voltage between 8 V and 14 V.
VOUT 9 O Output voltage. Connect any external output capacitors between these pins and PGND.