SLUSF87 February   2024 TPSM8S6B24S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Average Current-Mode Control
        1. 6.3.1.1 On-Time Modulator
        2. 6.3.1.2 Current Error Integrator
        3. 6.3.1.3 Voltage Error Integrator
      2. 6.3.2  Linear Regulators
      3. 6.3.3  AVIN and PVIN Pins
      4. 6.3.4  Input Undervoltage Lockout (UVLO)
        1. 6.3.4.1 Fixed AVIN UVLO
        2. 6.3.4.2 Fixed VDD5 UVLO
        3. 6.3.4.3 Programmable PVIN UVLO
        4. 6.3.4.4 EN/UVLO Pin
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Differential Sense Amplifier and Feedback Divider
      7. 6.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 6.3.7.1 Reset Output Voltage
        2. 6.3.7.2 Soft Start
      8. 6.3.8  Prebiased Output Start-Up
      9. 6.3.9  Soft Stop and (65h) TOFF_FALL Command
      10. 6.3.10 Power Good (PGOOD)
      11. 6.3.11 Set Switching Frequency
      12. 6.3.12 Frequency Synchronization
      13. 6.3.13 Loop Follower Detection
      14. 6.3.14 Current Sensing and Sharing
      15. 6.3.15 Telemetry
      16. 6.3.16 Overcurrent Protection
      17. 6.3.17 Overvoltage, Undervoltage Protection
      18. 6.3.18 Overtemperature Management
      19. 6.3.19 Fault Management
      20. 6.3.20 Back-Channel Communication
      21. 6.3.21 Switching Node (SW)
      22. 6.3.22 PMBus® General Description
      23. 6.3.23 PMBus® Address
      24. 6.3.24 PMBus® Connections
    4. 6.4 Device Functional Modes
      1. 6.4.1 Programming Mode
      2. 6.4.2 Standalone, Loop Controller, Loop Follower Mode Pin Connections
      3. 6.4.3 Continuous Conduction Mode
      4. 6.4.4 Operation With CNTL Signal (EN/UVLO)
      5. 6.4.5 Operation with (01h) OPERATION Control
      6. 6.4.6 Operation with CNTL and (01h) OPERATION Control
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus Commands
      2. 6.5.2 Pin Strapping
        1. 6.5.2.1 Programming MSEL1
        2. 6.5.2.2 Programming MSEL2
        3. 6.5.2.3 Programming VSEL
        4. 6.5.2.4 Programming ADRSEL
        5. 6.5.2.5 Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5)
        6. 6.5.2.6 Pin-Strapping Resistor Configuration
  8. 7 Register Maps
    1. 7.1  Conventions for Documenting Block Commands
    2. 7.2  (01h) OPERATION
    3. 7.3  (02h) ON_OFF_CONFIG
    4. 7.4  (03h) CLEAR_FAULTS
    5. 7.5  (04h) PHASE
    6. 7.6  (10h) WRITE_PROTECT
    7. 7.7  (15h) STORE_USER_ALL
    8. 7.8  (16h) RESTORE_USER_ALL
    9. 7.9  (19h) CAPABILITY
    10. 7.10 (1Bh) SMBALERT_MASK
    11. 7.11 (1Bh) SMBALERT_MASK_VOUT
    12. 7.12 (1Bh) SMBALERT_MASK_IOUT
    13. 7.13 (1Bh) SMBALERT_MASK_INPUT
    14. 7.14 (1Bh) SMBALERT_MASK_TEMPERATURE
    15. 7.15 (1Bh) SMBALERT_MASK_CML
    16. 7.16 (1Bh) SMBALERT_MASK_OTHER
    17. 7.17 (1Bh) SMBALERT_MASK_MFR
    18. 7.18 (20h) VOUT_MODE
    19. 7.19 (21h) VOUT_COMMAND
    20. 7.20 (22h) VOUT_TRIM
    21. 7.21 (24h) VOUT_MAX
    22. 7.22 (25h) VOUT_MARGIN_HIGH
    23. 7.23 (26h) VOUT_MARGIN_LOW
    24. 7.24 (27h) VOUT_TRANSITION_RATE
    25. 7.25 (29h) VOUT_SCALE_LOOP
    26. 7.26 (2Bh) VOUT_MIN
    27. 7.27 (33h) FREQUENCY_SWITCH
    28. 7.28 (35h) VIN_ON
    29. 7.29 (36h) VIN_OFF
    30. 7.30 (37h) INTERLEAVE
    31. 7.31 (38h) IOUT_CAL_GAIN
    32. 7.32 (39h) IOUT_CAL_OFFSET
    33. 7.33 (40h) VOUT_OV_FAULT_LIMIT
    34. 7.34 (41h) VOUT_OV_FAULT_RESPONSE
    35. 7.35 (42h) VOUT_OV_WARN_LIMIT
    36. 7.36 (43h) VOUT_UV_WARN_LIMIT
    37. 7.37 (44h) VOUT_UV_FAULT_LIMIT
    38. 7.38 (45h) VOUT_UV_FAULT_RESPONSE
    39. 7.39 (46h) IOUT_OC_FAULT_LIMIT
    40. 7.40 (47h) IOUT_OC_FAULT_RESPONSE
    41. 7.41 (4Ah) IOUT_OC_WARN_LIMIT
    42. 7.42 (4Fh) OT_FAULT_LIMIT
    43. 7.43 (50h) OT_FAULT_RESPONSE
    44. 7.44 (51h) OT_WARN_LIMIT
    45. 7.45 (55h) VIN_OV_FAULT_LIMIT
    46. 7.46 (56h) VIN_OV_FAULT_RESPONSE
    47. 7.47 (58h) VIN_UV_WARN_LIMIT
    48. 7.48 (60h) TON_DELAY
    49. 7.49 (61h) TON_RISE
    50. 7.50 (62h) TON_MAX_FAULT_LIMIT
    51. 7.51 (63h) TON_MAX_FAULT_RESPONSE
    52. 7.52 (64h) TOFF_DELAY
    53. 7.53 (65h) TOFF_FALL
    54. 7.54 (78h) STATUS_BYTE
    55. 7.55 (79h) STATUS_WORD
    56. 7.56 (7Ah) STATUS_VOUT
    57. 7.57 (7Bh) STATUS_IOUT
    58. 7.58 (7Ch) STATUS_INPUT
    59. 7.59 (7Dh) STATUS_TEMPERATURE
    60. 7.60 (7Eh) STATUS_CML
    61. 7.61 (7Fh) STATUS_OTHER
    62. 7.62 (80h) STATUS_MFR_SPECIFIC
    63. 7.63 (88h) READ_VIN
    64. 7.64 (8Bh) READ_VOUT
    65. 7.65 (8Ch) READ_IOUT
    66. 7.66 (8Dh) READ_TEMPERATURE_1
    67. 7.67 (98h) PMBUS_REVISION
    68. 7.68 (99h) MFR_ID
    69. 7.69 (9Ah) MFR_MODEL
    70. 7.70 (9Bh) MFR_REVISION
    71. 7.71 (9Eh) MFR_SERIAL
    72. 7.72 (ADh) IC_DEVICE_ID
    73. 7.73 (AEh) IC_DEVICE_REV
    74. 7.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
    75. 7.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
    76. 7.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
    77. 7.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
    78. 7.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
    79. 7.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
    80. 7.80 (E3h) MFR_SPECIFIC_19 (PGOOD_CONFIG)
    81. 7.81 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
    82. 7.82 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
    83. 7.83 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
    84. 7.84 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
    85. 7.85 (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS)
    86. 7.86 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
    87. 7.87 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
    88. 7.88 (FAh) MFR_SPECIFIC_42 (PASSKEY)
    89. 7.89 (FBh) MFR_SPECIFIC_43 (EXT_WRITE_PROTECT)
    90. 7.90 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
    91. 7.91 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Setting (VSEL Pin)
        4. 8.2.2.4  Compensation Selection (MSEL1 Pin)
        5. 8.2.2.5  Output Capacitor Selection
          1. 8.2.2.5.1 Output Voltage Ripple
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        8. 8.2.2.8  Enable and UVLO
        9. 8.2.2.9  ADRSEL
        10. 8.2.2.10 BCX_CLK and BCX_DAT
      3. 8.2.3 Application Curves
    3. 8.3 Two-Phase Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Two-Phase Detailed Design Procedure
        1. 8.3.2.1  Switching Frequency
        2. 8.3.2.2  Output Voltage Setting (VSEL Pin)
        3. 8.3.2.3  Compensation Selection (MSEL1 Pin)
        4. 8.3.2.4  Output Capacitor Selection
        5. 8.3.2.5  Input Capacitor Selection
        6. 8.3.2.6  GOSNS/Loop Follower Pin of Loop Follower Devices
        7. 8.3.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        8. 8.3.2.8  Enable, UVLO
        9. 8.3.2.9  VSHARE Pin
          1. 8.3.2.9.1 ADRSEL Pin
        10. 8.3.2.10 SYNC Pin
        11. 8.3.2.11 VOSNS Pin of Loop Follower Devices
        12. 8.3.2.12 Unused Pins of Loop Follower Devices
      3. 8.3.3 Two-Phase Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Performance on the TI EVM
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Texas Instruments Fusion Digital Power Designer
        2. 9.1.2.2 Custom Design With WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.27 (33h) FREQUENCY_SWITCH

CMD Address33h
Write Transaction:Write Word
Read Transaction:Read Word
Format:SLINEAR11, per CAPABILITY
Phased:No
Updates:Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. To update hardware after write while enabled, store to NVM with STORE_USER_ALL and RESTORE_USER_ALL or cycle AVIN below UVLO.
NVM Back-up:EEPROM or Pin Detection

FREQUENCY_SWITCH sets the switching frequency of the active channel in kHz.

Figure 7-26 (33h) FREQUENCY_SWITCH Register Map
15141312111098
RWRWRWRWRWRWRWRW
FSW_EXPFSW_MAN
76543210
RWRWRWRWRWRWRWRW
FSW_MAN
LEGEND: R/W = Read/Write; R = Read only
Table 7-24 Register Field Descriptions
BitFieldAccessResetDescription
15:11FSW_ EXPRWNVMLinear format two’s complement exponent
On reset, FSW_EXP is auto-generated based on the switching frequency stored in NVM.
10:0FSW_ MANRWNVMLinear format two’s complement mantissa. Refer to Table 7-25.
Table 7-25 Supported Switching Frequency Settings
FREQUENCY_SWITCH (Decoded)Effective Switching Frequency (kHz)
Less than 250 kHz225
251 ≤ FSW < 300 kHz275
301 ≤ FSW < 350 kHz325
351 ≤ FSW < 410 kHz375
411 ≤ FSW < 500 kHz450
501 ≤ FSW < 600 kHz550
601 ≤ FSW < 700 kHz650
701 ≤ FSW < 820 kHz750
821 ≤ FSW < 1000 kHz900
1001 ≤ FSW < 1200 kHz1100
1201 ≤ FSW < 1400 kHz1300
1401 ≤ FSW < 1650 kHz1500

FREQUENCY_SWITCH values greater than 1100 kHz can require higher VDD5 current than can be provided by the internal AVIN to VDD5 linear regulator. Programming FREQUENCY_SWITCH to a value greater than 1100 kHz without an external source to VDD5 can result in repeated start-up and shut-down attempt. FRQUENCY_SWITCH values greater than 1100 kHz are not recommended for Stacked Multi-phase operation.