SLUSF87 February 2024 TPSM8S6B24S
PRODUCTION DATA
The TPSM8S6B24S device uses an average current-mode control architecture with independently programmable current error integration and voltage error integration loops. This architecture provides similar performance to peak current-mode control without restricting the minimum on time or minimum off time control, allowing the gain selection of the current loop to effectively set the slope compensation. For help selecting compensation values, customers can use the TPSM8S6x24 Compensation and Pin-Strap Resistor Calculator design tool.