SLLSF73C February   2018  – September 2019 TS3USBCA4

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V)
    6. 6.6  Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    7. 6.7  Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    8. 6.8  Timing Requirements (3 V ≤ VCC ≤ 3.6 V)
    9. 6.9  Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Audio Path
      2. 8.3.2 High-Speed Paths
      3. 8.3.3 3-level Input
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 TS3USBCA4 Registers
        1. 8.6.1.1 Revision_ID Register (Offset = 9h) [reset = 0h]
          1. Table 8. Revision_ID Register Field Descriptions
        2. 8.6.1.2 General_1 Register (Offset = Ah) [reset = 0h]
          1. Table 9. General_1 Register Field Descriptions
        3. 8.6.1.3 General_2 Register (Offset = Bh) [reset = 0h]
          1. Table 10. General_2 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2 Detailed Design Procedure

The design procedure starts with the choice of supply. TS3USBCA4 wide supply range from 2.4 V to 5.5 V gives the designer flexibility when selecting a supply. Examples include, but are not limited to, a single-cell battery, a 3.3-V regulator, or VBUS. The designer must account for the parametric variation of TS3USBCA4 with supply range, the supply range of other components in the system, the IO voltage levels of companion devices, and cost. For example, a regulated 3.3-V VCC has the advantage of smaller variation of TS3USBCA4 performance compared to a single-cell batter between 2.7 V and 4.3 V. This regulator may add to the system cost and board area.

The next step in the design procedure is to choose between I2C- and pin-configuration mode. The I2C-configuration mode is preferred because it reduces the number of IOs needed from the micro-processor. Note that in TS3USBCA420 the flip functionality is only available in the I2C-configuration mode. The designer can choose from two I2C slave addresses through pin-strapping of I2C_EN to avoid address conflict. The IOs of TS3USBCA4 have well-controlled VIH and VIL and are supposed to work with a wide range of IO voltage levels of the micro-processor. However, the designer needs to check the compatibility of the IOs between the micro-processor and TS3USBCA4, and insert level translators when necessary.

In I2C-configuration mode, when it is necessary to set I2C_EN to the middle level to avoid slave address conflict, it is desirable to use as high a resistor value as possible for the resistor divider to minimize the static current through the resistor divider. However, the designer needs to take into account the resistor tolerance and the effect of the on-chip pull-down resistor to ensure a satisfactory voltage margin for VIM of the I2C_EN pin.

It should be noted that the bandwidth of the high-speed lanes is defined with the audio channel open. Due to the low RON of the audio channel, big parasitic capacitance exists between the audio output port and the SBU port. The load (capacitive and/or resistive) at the audio output port may significantly impact the bandwidth of the high-speed lanes. If bandwidth is importance, the audio channel is preferred. If certain high-speed signals have to go through the high-speed lanes, care should be taken to minimize the load at the audio output port, including the traces.