SLLSF73C February   2018  – September 2019 TS3USBCA4

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (3 V ≤ VCC ≤ 3.6 V)
    6. 6.6  Electrical Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    7. 6.7  Switching Characteristics (2.4 V ≤ VCC ≤ 5.5 V)
    8. 6.8  Timing Requirements (3 V ≤ VCC ≤ 3.6 V)
    9. 6.9  Timing Requirements (2.4 V ≤ VCC ≤ 5.5 V)
    10. 6.10 Timing Diagrams
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Audio Path
      2. 8.3.2 High-Speed Paths
      3. 8.3.3 3-level Input
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 TS3USBCA4 Registers
        1. 8.6.1.1 Revision_ID Register (Offset = 9h) [reset = 0h]
          1. Table 8. Revision_ID Register Field Descriptions
        2. 8.6.1.2 General_1 Register (Offset = Ah) [reset = 0h]
          1. Table 9. General_1 Register Field Descriptions
        3. 8.6.1.3 General_2 Register (Offset = Bh) [reset = 0h]
          1. Table 10. General_2 Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Programming

The TS3USBCA4 can be controlled using I2C. The SCL and SDA terminals are used for I2C clock and I2C data respectively.

Table 5. TS3USBCA4 I2C Slave Address

ADDR Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W/R)
ADDR0 1 0 1 1 1 0 0 0/1
ADDR1 1 0 1 1 1 0 1 0/1

The following procedure should be followed to write to TS3USBCA4 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a zero-value “W/R” bit to indicate a write cycle
  2. The TS3USBCA4 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte of data, MSB-first.
  4. The TS3USBCA4 acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The TS3USBCA4 acknowledges the byte transfer.
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TS3USBCA4.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TS3USBCA4 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a one-value “W/R” bit to indicate a read cycle
  2. The TS3USBCA4 acknowledges the address cycle.
  3. The TS3USBCA4 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the I2C.register occurred prior to the read, then the TS3USBCA4 shall start at the sub-address specified in the write.
  4. The TS3USBCA4 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the TS3USBCA4 transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the TS3USBCA4 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TS3USBCA4 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within TS3USBCA4) to be written, consisting of one byte of data, MSB-first.
  4. The TS3USBCA4 acknowledges the sub-address cycle.
  5. The master terminates the write operation by generating a stop condition (P).

NOTE

Upon reset, the TS3USBCA4 sub-address is always set to 0x00. The TS3USBCA4 increments the sub-address by one after each successful read or write transaction, so that the next read transaction that does not explicitly specify the sub-address will start from the next register.