SLUSCU6C August   2017  – January 2020 UCC256301

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Hybrid Hysteretic Control
      2. 7.3.2  Regulated 12-V Supply
      3. 7.3.3  Feedback Chain
      4. 7.3.4  Optocoupler Feedback Signal Input and Bias
      5. 7.3.5  System External Shut Down
      6. 7.3.6  Pick Lower Block and Soft Start Multiplexer
      7. 7.3.7  Pick Higher Block and Burst Mode Multiplexer
      8. 7.3.8  VCR Comparators
      9. 7.3.9  Resonant Capacitor Voltage Sensing
      10. 7.3.10 Resonant Current Sensing
      11. 7.3.11 Bulk Voltage Sensing
      12. 7.3.12 Output Voltage Sensing
      13. 7.3.13 High Voltage Gate Driver
      14. 7.3.14 Protections
        1. 7.3.14.1 ZCS Region Prevention
        2. 7.3.14.2 Over Current Protection (OCP)
        3. 7.3.14.3 Over Output Voltage Protection (VOUTOVP)
        4. 7.3.14.4 Over Input Voltage Protection (VINOVP)
        5. 7.3.14.5 Under Input Voltage Protection (VINUVP)
        6. 7.3.14.6 Boot UVLO
        7. 7.3.14.7 RVCC UVLO
        8. 7.3.14.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Burst Mode Control
      2. 7.4.2 High Voltage Start-Up
      3. 7.4.3 X-Capacitor Discharge
      4. 7.4.4 Soft-Start and Burst-Mode Threshold
      5. 7.4.5 System States and Faults State Machine
      6. 7.4.6 Waveform Generator State Machine
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  LLC Power Stage Requirements
        2. 8.2.2.2  LLC Gain Range
        3. 8.2.2.3  Select Ln and Qe
        4. 8.2.2.4  Determine Equivalent Load Resistance
        5. 8.2.2.5  Determine Component Parameters for LLC Resonant Circuit
        6. 8.2.2.6  LLC Primary-Side Currents
        7. 8.2.2.7  LLC Secondary-Side Currents
        8. 8.2.2.8  LLC Transformer
        9. 8.2.2.9  LLC Resonant Inductor
        10. 8.2.2.10 LLC Resonant Capacitor
        11. 8.2.2.11 LLC Primary-Side MOSFETs
        12. 8.2.2.12 Design Considerations for Adaptive Dead-Time
        13. 8.2.2.13 LLC Rectifier Diodes
        14. 8.2.2.14 LLC Output Capacitors
        15. 8.2.2.15 HV Pin Series Resistors
        16. 8.2.2.16 BLK Pin Voltage Divider
        17. 8.2.2.17 BW Pin Voltage Divider
        18. 8.2.2.18 ISNS Pin Differentiator
        19. 8.2.2.19 VCR Pin Capacitor Divider
        20. 8.2.2.20 Burst Mode Programming
        21. 8.2.2.21 Soft-Start Capacitor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 VCC Pin Capacitor
    2. 9.2 Boot Capacitor
    3. 9.3 RVCC Pin Capacitor
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support (if applicable)
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.5 System States and Faults State Machine

Below is an overview of the system states sequence:

The state transition diagram starts from the un-powered condition of UCC25630. As soon as the system is plugged in, HV pin JFET will be enabled and will start to deliver current from a source connected to the HV pin to the VCC capacitor. Once the VCC pin voltage exceeds its VCCStartSwitching threshold, system state will change to JFETOFF. When PFC output voltage reaches a certain level, LLC is turned on. Before LLC starts running, the LO pin is kept high to pull the HS node of the LLC bridge low, thus allowing the capacitor between HB and HS pins to be charged from VCC via the bootstrap diode. UCC256301 will remain in the CHARGE_BOOT state for a certain time to ensure the boot capacitor is fully charged. When LLC output voltage reaches a certain level, both PFC and LLC gets power from LLC transformer bias winding. When the load drops to below a certain level, LLC operates in burst mode

Fault conditions encountered by UCC256301 will cause operation to stop, or paused for a certain period of time followed by an automatic re-start. It is to ensure that while a persistent fault condition is present, it is not possible for UCC256301 or the power converter temperature to continue to rise as a result of the repeated re-start attempts.

UCC256301 sluscu6_block_diagram_system_states.gifFigure 49. Block Diagram of System States and Faults State Machine

Table 1 summarizes the inputs and outputs of Figure 49

Table 1. System States and Faults State Machine Block Inputs and Outputs

SIGNAL NAME I/O DESCRIPTION
OVP I Output over voltage fault
OTP I Over temperature fault
OCP1 I Peak current fault
OCP2 I Average current fault with 2ms timer
OCP3 I Average current fault with 50ms timer
BLKStart I Bulk voltage is above start threshold
BLKStop I Bulk voltage is below stop threshold
BLKOV I Bulk over voltage fault
RVCCUVLO I RVCC UVLO fault
VCCReStartJfet I VCC is below restart threshold
VCCStartSwitching I VCC is above start switching threshold (the threshold is different in self bias mode and external bias mode)
ACZeroCrossing I AC zero crossing is detected
FBLessThanBMT I FBReplica voltage is less than burst mode threshold
WaveGenEn O Waveform generator enable
RVCCEn O RVCC enable
VCCClampEn O Enable VCC clamp mode (details in VCC pin section)
SSEn O Soft start enable
XcapDischarge O Activate x-cap discharge
HVFetOn O Turn on or off JFET

The state machine is shown in Figure 50 and the description of the states and state transition conditions are in the tables below.

UCC256301 fig36_sluscu6.gifFigure 50. System States and Faults State Machine

Table 2. States in System States and Faults State Machine(1)

STATE OUTPUT STATUS DESCRIPTION
STARTUP WaveGenEn = 0
RVCCEn = 0
VCCClampEn = 1
SSEn = 0
HVFetOn = 1 		This is the first state after power on reset (POR). In this state, the HV JEFT is on, and it’s working in a voltage clamp state where the VCC voltage is regulated to 13V to allow internal circuits to load trim settings and start up.
JFETON WaveGenEn = 0
RVCCEn = 0
VCCClampEn = 0
SSEn = 0
HVFetOn = 1 		In this state, the JFET is on. The VCC clamp mode is disabled. HV start up current is regulated to IHVHigh.
JFETOFF WaveGenEn = 0
RVCCEn = 1
VCCClampEn = 0
SSEn = 0
HVFetOn = 0 		When VCC is higher than VCCStartSwitching threshold, the JFET is turned off and system enters JFETOFF state. The regulated RVCC is turned on. PFC soft start begins.
WAKEUP WaveGenEn = 0
RVCCEn = 1
VCCClampEn = 0
SSEn = 0
HVFetOn = 0 		When BLK voltage reaches BLKStart level, the system enters WAKEUP state and stay in WAKEUP state for 150us for the analog circuits to wake up.
CHARGE_BOOT WaveGenEn = 0
RVCCEn = 1
VCCClampEn = 0
SSEn = 0
HVFetOn = 0 		In this state, the BOOT capacitor is charged by turning on the low side switch for a certain period of time.
STEADY_STATE_RUN WaveGenEn = 1
RVCCEn = 1
VCCClampEn = 0
SSEn = 1
HVFetOn = 0 		In this state, the waveform generator is enabled. Soft start module is enabled. LLC starts to soft start. When soft start is done, the system enters normal operation.
LIGHT_LOAD_RUN WaveGenEn = 1
RVCCEn = 1
VCCClampEn = 0
SSEn = 1
HVFetOn = 0 		If FBReplica is less than burst mode threshold during normal operation, the system enters LIGHT_LOAD_RUN mode. The FBLessThanBMT time is counted. If the time is longer than 200ms, it is treated as a fault, restart the system.
FAULT WaveGenEn = 0
RVCCEn = 0
VCCClampEn = 0
SSEn = 0
HVFetOn = 0 		After any fault condition, the system enters FAULT state and waits for 1s before re-start. The 1s timer allows system to cool down and prevents frequent repetitive start up in case of a persistent fault.
(1) XCapacitor discharge is dependent on AC unplug detection, and it’s independent on the system states and faults state machine. The details have been discussed in X-Capacitor Discharge and are not captured in this table.

Table 3. System States and Faults State Machine State Transition Conditions

STATE TRANSITION CONDITION DESCRIPTION
1 System ready (trim load done)
2 VCCStartSwitching = 1
VCCReStartJfet = 0
3 BLKStart = 1
BLKStop = 0
BLKOV = 0
RVCCUVLO = 0
4 BLKStart = 1
BLKStop = 0
BLKOV = 0
RVCCUVLO = 0
FBLessThanBMT = 0
5 Charge boot done
6 FBLessThanBMT = 1
7 FBLessThanBMT = 0
8 VCCReStartJfet = 1
9 VCCReStartJfet = 1
10 VCCReStartJfet = 1
11 VCCReStartJfet = 1
12 VCCReStartJfet = 1
13 FBLessThanBMT time out
14 BLKOV = 1
15 BLKOV = 1
16 OTP = 1 or BLKOV = 1 or
BLKStop = 1 or OVP or OCP1 or OCP2 time out or
OCP3 time out or RVCCUVLO = 1
17 OTP = 1 or BLKOV = 1 or
BLKStop = 1 or OVP or OCP1 or OCP2 time out or
OCP3 time out or RVCCUVLO = 1
18 OTP = 1
19 OTP = 1
20 OTP = 1
21 OTP = 1
22 OTP = 1
23 1s pause time out

Figure 51 only shows the most commonly used state transition (assuming no faults during start up states so all the states are captured in the timing diagram). Many different ways of state transitions may happen according to the state machine, but are not captured in this section.

In Figure 51, a normal start up procedure is shown. The system enters normal operation and then a fault (OCP, OVP, or OTP) happens.

NOTE

OCP1 and OVP are fast faults and are first processed in the waveform generator state machine.

The system is configured to be restart after 1s pause time.

UCC256301 fig51_sluscu6.gifFigure 51. Timing Diagram of System States and Faults