SLUSD90D May   2019  – November 2020 UCC256402 , UCC256403 , UCC256404

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
    1.     Device Comparison Table
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hybrid Hysteretic Control
      2. 7.3.2 Regulated 13-V Supply
      3. 7.3.3 Feedback Chain
        1. 7.3.3.1 Optocoupler Feedback Signal Input and Bias
        2. 7.3.3.2 FB Pin Voltage Clamp
        3. 7.3.3.3 "Pick Lower Value" Block and Soft Start Multiplexer
        4. 7.3.3.4 Pick Higher Block and Burst Mode Multiplexer
        5. 7.3.3.5 VCR Comparators
      4. 7.3.4 Resonant Capacitor Voltage Sensing
      5. 7.3.5 Resonant Current Sensing
      6. 7.3.6 Bulk Voltage Sensing
      7. 7.3.7 Output Voltage Sensing
      8. 7.3.8 High Voltage Gate Driver
        1. 7.3.8.1 Adaptive Dead Time Control
      9. 7.3.9 Protections
        1. 7.3.9.1 ZCS Region Prevention
        2. 7.3.9.2 Over Current Protection (OCP)
        3. 7.3.9.3 Bias Winding Over Voltage Protection (BWOVP)
        4. 7.3.9.4 Input Under Voltage Protection (VINUVP)
        5. 7.3.9.5 Input Over Voltage Protection (VINOVP)
        6. 7.3.9.6 Boot UVLO
        7. 7.3.9.7 RVCC UVLO
        8. 7.3.9.8 Over Temperature Protection (OTP)
    4. 7.4 Device Functional Modes
      1. 7.4.1 High Voltage Start-Up
      2. 7.4.2 X-Capacitor Discharge
      3. 7.4.3 Burst Mode Control
        1. 7.4.3.1 Soft-Start and Burst-Mode Threshold
        2. 7.4.3.2 BMTL/BMTH Ratio Programming
      4. 7.4.4 System State Machine
  8. Power Supply Recommendations
    1. 8.1 VCC Pin Capacitor
    2. 8.2 Boot Capacitor
    3. 8.3 RVCC Pin Capacitor
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Related Links
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

ZCS Region Prevention

The capacitive region is an LLC operating region in which the voltage gain increases when the switching frequency increases. It is also called the ZCS region. Capacitive mode operation should be avoided for two reasons:

  • The feedback loop becomes positive feedback in the capacitive region
  • The MOSFET may be damaged because of body diode reverse recovery

The capacitive region detection is done by checking the resonant current polarity at HSON or LSON falling edge. If the resonant current is positive at LSON falling edge, or negative at HSON falling edge, the ZCS signal in the waveform generator is turned high. The ZCS signal stays high until ZCS is cleared at the next HSON or LSON falling edge.

If ZCS is detected, the next gate will be turned on at the next IPolarity flip event when the resonant current becomes inductive again. The IPolarity flip indicates that the capacitive operation cycle has already passed. The resonant current reverses direction and begins to discharge the switch node. In this stage, the body diode is no longer conducting and it is allowed to turn on the next gate. If there is a slew done event detected, it suggests that the opposite body diode must not be conducting and the next gate will be turned on as well. If neither the IPolarity flip event or slew done event is detected, the next gate will be turned on by the maximum dead time timer expiration. During a ZCS event, the maximum dead time is changed to 150 µs.

ZCS typically happens when the LLC operates at heavy load condition and the switching frequency is too low. Therefore, when ZCS is detected, the LL/SS pin is pulled low through a diode to ground and the system enters a "ZCS soft start" process. The switching frequency is forced to ramp up in order for the system to recover from ZCS. The details of the "ZCS soft start" are described in the Section 7.4.3.1 section. As the ZCS detection relies on the resonant current polarity detection, if LLC operates at very light load condition, the magnitude of the resonant current can be very small and there may be chances that the resonant current polarity detection can be distorted by the switching noise. In order to prevent the nuisance ZCS detection at light load condition, ZCS is disabled at light load condition by utilizing the burst mode control. The details are described in the Section 7.4.3 section.

Below is the flow chart of the capacitive region prevention algorithm and the timing diagram of a ZCS event:

GUID-7CACCB2D-B9F0-43F4-9120-C3CE1176FE61-low.gifFigure 7-11 ZCS Prevention Algorithm Flow Chart
GUID-19A87D7E-9EB5-4A48-B710-B432A4361675-low.gifFigure 7-12 Timing Diagram of a ZCS Event