SLUSAP2I March   2012  – January 2017 UCD3138

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison Table
    1. 3.1 Product Family Comparison
    2. 3.2 Product Selection Matrix
  4. Pin Configuration and Functions
    1. 4.1 UCD3138RGC 64 QFN Pin Attributes
    2. 4.2 UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing and Switching Characteristics
    7. 5.7 Power Supply Sequencing
    8. 5.8 Peripherals
      1. 5.8.1 Digital Power Peripherals (DPPs)
        1. 5.8.1.1 Front End
        2. 5.8.1.2 DPWM Module
        3. 5.8.1.3 DPWM Events
        4. 5.8.1.4 High Resolution DPWM
        5. 5.8.1.5 Oversampling
        6. 5.8.1.6 DPWM Interrupt Generation
        7. 5.8.1.7 DPWM Interrupt Scaling/Range
    9. 5.9 Typical Temperature Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
      1. 6.3.1 CPU Memory Map and Interrupts
      2. 6.3.2 Boot ROM
      3. 6.3.3 Customer Boot Program
      4. 6.3.4 Flash Management
    4. 6.4 System Module
      1. 6.4.1 Address Decoder (DEC)
      2. 6.4.2 Memory Management Controller (MMC)
      3. 6.4.3 System Management (SYS)
      4. 6.4.4 Central Interrupt Module (CIM)
    5. 6.5 Feature Description
      1. 6.5.1  Sync FET Ramp and IDE Calculation
      2. 6.5.2  Automatic Mode Switching
        1. 6.5.2.1 Phase Shifted Full Bridge Example
        2. 6.5.2.2 LLC Example
        3. 6.5.2.3 Mechanism for Automatic Mode Switching
      3. 6.5.3  DPWMC, Edge Generation, IntraMux
      4. 6.5.4  Filter
        1. 6.5.4.1 Loop Multiplexer
        2. 6.5.4.2 Fault Multiplexer
      5. 6.5.5  Communication Ports
        1. 6.5.5.1 SCI (UART) Serial Communication Interface
        2. 6.5.5.2 PMBUS
        3. 6.5.5.3 General Purpose ADC12
        4. 6.5.5.4 Timers
          1. 6.5.5.4.1 24-bit PWM Timer
          2. 6.5.5.4.2 16-Bit PWM Timers
          3. 6.5.5.4.3 Watchdog Timer
      6. 6.5.6  Miscellaneous Analog
      7. 6.5.7  Package ID Information
      8. 6.5.8  Brownout
      9. 6.5.9  Global I/O
      10. 6.5.10 Temperature Sensor Control
      11. 6.5.11 I/O Mux Control
      12. 6.5.12 Current Sharing Control
      13. 6.5.13 Temperature Reference
    6. 6.6 Device Functional Modes
      1. 6.6.1 Normal Mode
      2. 6.6.2 Phase Shifting
      3. 6.6.3 DPWM Multiple Output Mode
      4. 6.6.4 DPWM Resonant Mode
      5. 6.6.5 Triangular Mode
      6. 6.6.6 Leading Edge Mode
  7. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
        3. 7.2.2.3 DPWM Synchronization
        4. 7.2.2.4 Fixed Signals to Bridge
        5. 7.2.2.5 Dynamic Signals to Bridge
        6. 7.2.2.6 System Initialization for PCM
          1. 7.2.2.6.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.6.2 Peak Current Detection
          3. 7.2.2.6.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
  8. Power Supply Recommendations
    1. 8.1 Power Supply Decoupling and Bulk Capacitors
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Tools and Documentation
    2. 10.2 Documentation Support
      1. 10.2.1 References
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical Packaging and Orderable Information
    1. 11.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Device Overview

Features

  • Digital Control of up to 3 Independent Feedback Loops
    • Dedicated PID-Based hardware
    • 2-Pole/2-Zero Configurable
    • Nonlinear Control
  • Up to 16 MHz Error Analog-to-Digital Converter (EADC)
    • Configurable Resolution as Small as 1mV/LSB
    • Automatic Resolution Selection
    • Up to 8x Oversampling
    • Hardware-Based Averaging (up to 8x)
    • 14-Bit Effective Digital-to-Analog Converter (DAC)
    • Adaptive Sample Trigger Positioning
  • Up to 8 High Resolution Digital Pulse Width Modulated (DPWM) Outputs
    • 250-ps Pulse Width Resolution
    • 4-ns Frequency Resolution
    • 4-ns Phase Resolution
    • Adjustable Phase Shift Between Outputs
    • Adjustable Dead-band Between Pairs
    • Cycle-by-Cycle Duty Cycle Matching
    • Up to 2-MHz Switching Frequency
  • Configurable PWM Edge Movement
    • Trailing Modulation
    • Leading Modulation
    • Triangular Modulation
  • Configurable Feedback Control
    • Voltage Mode
    • Average Current Mode
    • Peak Current Mode Control
    • Constant Current
    • Constant Power
  • Configurable Modulation Methods
    • Frequency Modulation
    • Phase Shift Modulation
    • Pulse Width Modulation
  • Fast, Automatic, and Smooth Mode Switching
    • Frequency Modulation and PWM
    • Phase Shift Modulation and PWM
  • High Efficiency and Light Load Management
    • Burst Mode
    • Ideal Diode Emulation
    • Synchronous Rectifier Soft On/Off
    • Low IC Standby Power
  • Soft Start / Stop with and without Prebias
  • Fast Input Voltage Feed Forward Hardware
  • Primary Side Voltage Sensing
  • Copper Trace Current Sensing
  • Flux and Phase Current Balancing for Nonpeak Current Mode Control Applications
  • Current Share Bus Support
    • Analog Average
    • Master and Slave
  • Feature Rich Fault Protection Options
    • 7 High-Speed Analog Comparators
    • Cycle-by-Cycle Current Limiting
    • Programmable Fault Counting
    • External Fault Inputs
    • 10 Digital Comparators
    • Programmable Blanking Time
  • Synchronization of DPWM Waveforms Between Multiple UCD3138 devices
  • 14-Channel, 12-Bit, 267-ksps General-Purpose ADC with Integrated
    • Programmable Averaging Filters
    • Dual Sample and Hold
  • Internal Temperature Sensor
  • Fully Programmable High-Performance 31.25 MHz, 32-Bit ARM7TDMI-S™ Processor
    • 32KB of Program Flash
    • 2KB of Data Flash with ECC
    • 4KB of Data RAM
    • 4KB of Boot ROM Enables Firmware Boot-Load in the Field via I2C or UART
  • Communication Peripherals
    • I2C/PMBus
    • 2 UARTs on UCD3138RGC (64-Pin QFN)
    • 1 UART on UCD3138RHA/UCD3138RMH
      (40-Pin QFN) and UCD3138RJA (40-Pin VQFN)
  • Timer Capture with Selectable Input Pins
  • Up to 5 Additional General Purpose Timers
  • Built In Watchdog: BOD and POR
  • 64-Pin QFN and 40-Pin QFN Packages
  • Operating Temperature: –40°C to 125°C
  • Fusion_Digital_Power_Designer GUI Support

Applications

  • Power Supplies and Telecom Rectifiers
  • Power Factor Correction
  • Isolated DC-DC Modules

Description

The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single-chip solution. The flexible nature of the UCD3138 makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC-DC and isolated DC-DC applications and reduce the solution component count in the IT and network infrastructure space.

The UCD3138 controller is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customers' development effort by offering best-in-class development tools, including application firmware, Code Composer Studio™ software development environment, and TI’s power development GUI which lets customers configure and monitor key system parameters.

At the core of the UCD3138 controller are the digital control loop peripherals, also known as Digital Power Peripherals (DPPs). Each DPP implements a high-speed digital control loop consisting of a dedicated Error Analog-to-Digital Converter (EADC), a PID-based 2-pole/2-zero digital compensator and DPWM outputs with 250-ps pulse width resolution. The device also contains a 12-bit, 267-ksps general-purpose ADC with up to 14 channels, timers, interrupt control, PMBus, and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals, and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on-chip RAM and ROM.

In addition to the FDPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, LLC and phase-shifted full bridge mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high-resolution current sharing, hardware-configurable soft start with pre bias, as well as several other features. Topology support has been optimized for voltage mode and peak current mode controlled phase-shifted full bridge, single and dual phase PFC, bridgeless PFC, hard-switched full bridge and half bridge, and LLC half bridge and full bridge.

Device Information(1)

PART NUMBER PACKAGE DRAWING PACKAGE TYPE BODY SIZE
UCD3138 RGC VQFN (64) 9.00 mm × 9.00 mm
RHA VQFN (40) 6.00 mm × 6.00 mm
RMH WQFN (40) 6.00 mm × 6.00 mm
RJA VQFN (40) (2) 6.00 mm × 6.00 mm
For more information, see Section 11, Mechanical Packaging and Orderable Information.
Recommended for new 40-pin designs, optimized for improved performance under temperature cycling test for board level reliability (BLR).

Functional Block Diagram

Figure 1-1 shows a functional block diagram of the device.

UCD3138 fbd4_lusap2.gif Figure 1-1 Functional Block Diagram

NOTE

Front-end 2 Recommended for Peak Current Mode Control