SLUSAP2J March 2012 – November 2021 UCD3138
PRODUCTION DATA
| PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENT | ||||||
| I33A | Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled | 6.3 | mA | |||
| I33DIO | All GPIO and communication pins are open | 0.35 | mA | |||
| I33D | ROM program execution | 60 | mA | |||
| I33D | Flash programming in ROM mode | 70 | mA | |||
| I33 | The device is in ROM mode with all DPWMs enabled and switching at 2 MHz. The DPWMs are all unloaded. | 100 | mA | |||
| ERROR ADC INPUTS EAP, EAN | ||||||
| EAP – AGND | –0.15 | 1.998 | V | |||
| EAP – EAN | –0.256 | 1.848 | V | |||
| Typical error range | AFE = 0 | –256 | 248 | mV | ||
| EAP – EAN Error voltage digital resolution | AFE = 3 | 0.8 | 1 | 1.20 | mV | |
| AFE = 2 | 1.7 | 2 | 2.30 | mV | ||
| AFE = 1 | 3.55 | 4 | 4.45 | mV | ||
| AFE = 0 | 6.90 | 8 | 9.10 | mV | ||
| REA | Input impedance (See Figure 8-4) | AGND reference | 0.5 | MΩ | ||
| IOFFSET | Input offset current (See Figure 8-4) | –5 | 5 | μA | ||
| EADC offset | Input voltage = 0 V at AFE = 0 | –2 | 2 | LSB | ||
| Input voltage = 0 V at AFE = 1 | –2.5 | 2.5 | LSB | |||
| Input voltage = 0 V at AFE = 2 | –3 | -3 | LSB | |||
| Input voltage = 0 V at AFE = 3 | –4 | 4 | LSB | |||
| Sample Rate | 16 | MHz | ||||
| Analog Front End Amplifier Bandwidth | 100 | MHz | ||||
| A0 | Gain | See Figure 8-5 | 1 | V/V | ||
| Minimum output voltage | 100 | mV | ||||
| EADC DAC | ||||||
| DAC range | 0 | 1.6 | V | |||
| VREF DAC reference resolution | 10 bit, No dithering enabled | 1.56 | mV | |||
| VREF DAC reference resolution | With 4 bit dithering enabled | 97.6 | μV | |||
| INL | –3.0 | 3.0 | LSB | |||
| DNL | Does not include MSB transition | –2.1 | 1.6 | LSB | ||
| DNL at MSB transition | –1.4 | LSB | ||||
| DAC reference voltage | 1.58 | 1.61 | V | |||
| τ | Settling Time | From 10% to 90% | 250 | ns | ||
| ADC12 | ||||||
| IBIAS | Bias current for PMBus address pins | 9.5 | 10.5 | μA | ||
| Measurement range for voltage monitoring | 0 | 2.5 | V | |||
| Internal ADC reference voltage | –40°C to 125°C | 2.475 | 2.500 | 2.525 | V | |
| Change in Internal ADC reference from 25°C reference voltage(1) | –40°C to 25°C | –0.4 | mV | |||
| 25°C to 85°C | –1.8 | |||||
| 25°C to 125°C | –4.2 | |||||
| ADC12 INL integral nonlinearity(1) | ADC_SAMPLINGSEL = 6 for all ADC12 data, 25 °C to 125 °C | ±2.5 | LSB | |||
| ADC12 DNL differential nonlinearity(1) | –0.7/+2.5 | LSB | ||||
| ADC Zero Scale Error | –7 | 7 | mV | |||
| ADC Full Scale Error | –35 | 35 | mV | |||
| Input bias | 2.5 V applied to pin | 400 | nA | |||
| Input leakage resistance(1) | ADC_SAMPLINGSEL= 6 or 0 | 1 | MΩ | |||
| Input Capacitance(1) | 10 | pF | ||||
| ADC single sample conversion time(1) | ADC_SAMPLINGSEL= 6 or 0 | 3.9 | μs | |||
| DIGITAL INPUTS/OUTPUTS(2)(3) | ||||||
| VOL | Low-level output voltage(4) | IOH = 4 mA, V33DIO = 3 V | DGND + 0.25 | V | ||
| VOH | High-level output voltage (4) | IOH = –4 mA, V33DIO = 3 V | V33DIO – 0.6 | V | ||
| VIH | High-level input voltage | V33DIO = 3 V | 2.1 | V | ||
| VIL | Low-level input voltage | V33DIO = 3 V | 1.1 | V | ||
| IOH | Output sinking current | 4 | mA | |||
| IOL | Output sourcing current | –4 | mA | |||
| SYSTEM PERFORMANCE | ||||||
| TWD | Watchdog time out range | Total time is: TWD × (WDCTRL.PERIOD + 1) | 14.6 | 17 | 20.5 | ms |
| Time to disable DPWM output based on active FAULT pin signal | High level on FAULT pin | 70 | ns | |||
| Processor master clock (MCLK) | 31.25 | MHz | ||||
| tDelay | Digital compensator delay(5) | (1 clock = 32 ns) | 6 | clocks | ||
| t(reset) | Pulse width needed at reset(1) | 10 | µs | |||
| Retention period of flash content (data retention and program) | TJ = 25°C | 100 | years | |||
| Program time to erase one page or block in data flash or program flash | 20 | ms | ||||
| Program time to write one word in data flash or program flash | 20 | µs | ||||
| f(PCLK) | Internal oscillator frequency | 240 | 250 | 260 | MHz | |
| Sync-in/sync-out pulse width | Sync pin | 256 | ns | |||
| Flash Read | 1 | MCLKs | ||||
| Flash Write | 20 | μs | ||||
| ISHARE | Current share current source (See Figure 9-16) | 238 | 259 | μA | ||
| RSHARE | Current share resistor (See Figure 9-16) | 9.75 | 10.3 | kΩ | ||
| POWER ON RESET AND BROWN OUT (V33D pin, See Figure 8-3) | ||||||
| VGH | Voltage good high | 2.7 | V | |||
| VGL | Voltage good low | 2.5 | V | |||
| Vres | Voltage at which IReset signal is valid | 0.8 | V | |||
| TPOR | Time delay after power is good or RESET* relinquished | 1 | ms | |||
| Brownout | Internal signal warning of brownout conditions | 2.9 | V | |||
| TEMPERATURE SENSOR(6) | ||||||
| VTEMP | Voltage range of sensor | 1.46 | 2.44 | V | ||
| Voltage resolution | V/°C | 5.9 | mV/°C | |||
| Temperature resolution | °C per bit | 0.1034 | °C/LSB | |||
| Accuracy(6)(7) | –40°C to 125°C | –10 | ±5 | 10 | °C | |
| Temperature range | –40°C to 125°C | –40 | 125 | °C | ||
| ITEMP | Current draw of sensor when active | 30 | μA | |||
| TON | Turn on time / settling time of sensor | 100 | μs | |||
| VAMB | Ambient temperature | Trimmed 25°C reading | 1.85 | V | ||
| ANALOG COMPARATOR | ||||||
| DAC | Reference DAC Range | 0 | 2.5 | V | ||
| Reference Voltage | 2.478 | 2.5 | 2.513 | V | ||
| Bits | 7 | bits | ||||
| INL(6) | –0.42 | 0.21 | LSB | |||
| DNL(6) | 0.06 | 0.12 | LSB | |||
| Offset | –5.5 | 19.5 | mV | |||
| Time to disable DPWM output based on 0 V to 2.5 V step input on the analog comparator.(1) | 150 | ns | ||||
| Reference DAC buffered output load(8) | 0.5 | 1 | mA | |||
| Buffer offset (–0.5 mA) | 4.6 | 8.3 | mV | |||
| Buffer offset (1.0 mA) | –0.05 | 17 | mV | |||