JAJSP77A November   2019  – August 2020 BQ79600-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 仕様
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Modes and Power Supply
        1. 7.3.1.1 Power Mode
        2. 7.3.1.2 Pings
        3. 7.3.1.3 SPI/UART の選択
        4. 7.3.1.4 Digital Reset
        5. 7.3.1.5 Power Mode in BMS System
        6. 7.3.1.6 Power Supply
        7. 7.3.1.7 Shutdown
      2. 7.3.2 Communication
        1. 7.3.2.1 Data Communication Protocol
          1. 7.3.2.1.1 Frame Layer
            1. 7.3.2.1.1.1 Calculating Frame CRC Value
            2. 7.3.2.1.1.2 Verifying Frame CRC
          2. 7.3.2.1.2 Physical Layer
            1. 7.3.2.1.2.1 UART
              1. 7.3.2.1.2.1.1 TX HOLD OFF
              2. 7.3.2.1.2.1.2 UART COMM CLEAR
            2. 7.3.2.1.2.2 SPI
              1. 7.3.2.1.2.2.1 SPI_RDY と SPI FIFO
              2. 7.3.2.1.2.2.2 Flow to Read/Write BQ79600-Q1
              3. 7.3.2.1.2.2.3 SPI COMM CLEAR
            3. 7.3.2.1.2.3 Daisy Chain
        2. 7.3.2.2 Tone Communication Protocol
        3. 7.3.2.3 Device Auto Addressing / Ring Communication
          1. 7.3.2.3.1 Auto-Addressing
          2. 7.3.2.3.2 Ring Communication (optional)
        4. 7.3.2.4 Communication Timeout
        5. 7.3.2.5 Communication Debug Mode
      3. 7.3.3 Fault Handling
        1. 7.3.3.1 Fault Status Hierarchy/Reset/Mask
          1. 7.3.3.1.1 Fault Status Hierarchy
          2. 7.3.3.1.2 Fault Reset and Mask
        2. 7.3.3.2 Fault Interface
          1. 7.3.3.2.1 NFAULT
          2. 7.3.3.2.2 Daisy Chain (COMH and COML)
            1. 7.3.3.2.2.1 Fault Transmitting when BQ79600-Q1 in ACTIVE
            2. 7.3.3.2.2.2 Fault Transmitting when BQ79600-Q1 in SLEEP
            3. 7.3.3.2.2.3 Fault Transmitting (Automatic Host Wakeup/Reverse Wakeup) when BQ79600-Q1 in SHUTDOWN
      4. 7.3.4 INH/ Reverse Wakeup
      5. 7.3.5 Sniff Detector
      6. 7.3.6 Device Diagnostic
        1. 7.3.6.1 Power Supplies Check
          1. 7.3.6.1.1 Power Supply Diagnostic Check
          2. 7.3.6.1.2 Power Supply BIST
        2. 7.3.6.2 Thermal Shutdown
        3. 7.3.6.3 Oscillators Watchdog
        4. 7.3.6.4 Register Bit Flip Monitor
        5. 7.3.6.5 SPI FIFO 診断
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table
      2. 7.5.2  Register: DIR0_ADDR
      3. 7.5.3  Register: DIR1_ADDR
      4. 7.5.4  Register: CONTROL1
      5. 7.5.5  Register: CONTROL2
      6. 7.5.6  Register: DIAG_CTRL
      7. 7.5.7  Register: DEV_CONF1
      8. 7.5.8  Register: DEV_CONF2
      9. 7.5.9  Register: TX_HOLD_OFF
      10. 7.5.10 Register: SLP_TIMEOUT
      11. 7.5.11 Register: COMM_TIMEOUT
      12. 7.5.12 Register: SPI_FIFO_UNLOCK
      13. 7.5.13 Register: FAULT_MSK
      14. 7.5.14 Register: FAULT_RST
      15. 7.5.15 Register: FAULT_SUMMARY
      16. 7.5.16 Register: FAULT_REG
      17. 7.5.17 Register: FAULT_SYS
      18. 7.5.18 Register: FAULT_PWR
      19. 7.5.19 Register: FAULT_COMM1
      20. 7.5.20 Register: FAULT_COMM2
      21. 7.5.21 Register: DEV_DIAG_STAT
      22. 7.5.22 Register: PARTID
      23. 7.5.23 Register: DIE_ID1
      24. 7.5.24 Register: DIE_ID2
      25. 7.5.25 Register: DIE_ID3
      26. 7.5.26 Register: DIE_ID4
      27. 7.5.27 Register: DIE_ID5
      28. 7.5.28 Register: DIE_ID6
      29. 7.5.29 Register: DIE_ID7
      30. 7.5.30 Register: DIE_ID8
      31. 7.5.31 Register: DIE_ID9
      32. 7.5.32 Register: DEBUG_CTRL_UNLOCK
      33. 7.5.33 Register: DEBUG_COMM_CTRL
      34. 7.5.34 Register: DEBUG_COMM_STAT
      35. 7.5.35 Register: DEBUG_SPI_PHY
      36. 7.5.36 Register: DEBUG_SPI_FRAME
      37. 7.5.37 Register: DEBUG_UART_FRAME
      38. 7.5.38 Register: DEBUG_COMH_PHY
      39. 7.5.39 Register: DEBUG_COMH_FRAME
      40. 7.5.40 Register: DEBUG_COML_PHY
      41. 7.5.41 Register: DEBUG_COML_FRAME
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Bridge With Reverse Wakeup in UART
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 MCU Interface (UART, NFAULT)
          2. 8.2.1.2.2 Daisy Chain Interface
          3. 8.2.1.2.3 INH Connection
        3. 8.2.1.3 Application Performance Plot
      2. 8.2.2 Bridge Without Reverse Wakeup in SPI
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 MCU Interface (SPI, SPI_RDY, NFAULT)
          2. 8.2.2.2.2 Daisy Chain Interface
        3. 8.2.2.3 Application Performance Plot
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground Planes
      2. 10.1.2 Bypass Capacitors for Power Supplies
      3. 10.1.3 UART/SPI communication
      4. 10.1.4 Daisy Chain Communication
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions

PINTYPE(1)DESCRIPTION
NAMENO.
VIO3PPower supply input for UART/SPI input/output pins. Decouple with a 0.1μF capacitor to GND. VIO should be powered before SCLK, nCS, RX/MOSI, TX/MISO, NFAULT, nUART/SPI (SPI_RDY) is driven.
SCLK6DISPI clock input. If SPI interface is used, this pin is connected to SPI master controller. Connect to GND with a 10-100kohm pull-down resistor. If not used, connect to GND.
nCS7DIActive low chip select pin for SPI interface. Connect to VIO with 10-100kohm pull-up resistor in SPI mode. Cannot hardwire to GND in SPI mode. Connect to GND in UART mode.
RX/MOSI4DIUART receiver input or SPI master out slave in. Connect to VIO with a 10-100kohm pull-up resistor. Don't leave it unconnected.
TX/MISO5DOUART transmitter output or SPI master in slave out. Pull up to VIO with a 10-100kohm pull-up resistor at MCU side. MISO pin drives high in SPI idle mode, cannot directly support SPI multidrop, if multidrop is needed, add a tri-state buffer between BQ79600-Q1 and MCU.
NFAULT2DOFault indication output. Open drain active low. Pull up to VIO with 100kohm resistor. Connect NFAULT to host MCU GPIO. If not used, connect to GND.
nUART/SPI (SPI_RDY)8DI/OIf used as UART mode, connect this pin to GND. If used as SPI mode, connect to VIO through 10-100kohm pull up resistor and connect this pin to MCU GPIO. This pin is used as an input pin to select SPI or UART interface before device finishes wakeup/reset initialization (SPI communication is ready). If SPI mode is selected, SPI_RDY has to be used by host to decide if read/write can be initiated or needing further wait. Refer to Section 7.3.2.1.2.2.1 details.
DVDD1P1.8V regulated output. DVDD supplies the internal digital circuits. Bypass DVDD with a 0.22μF (recommended) or a 0.47μF capacitor to GND.
GND9PGround.
CVDD14PDedicated 5V supply used for the daisy chain communications. Decouple with a 0.22μF (recommended) or a 0.47μF to GND.
COMHN12AC-I/OThis is an AC coupled bi-directional I/O pin for daisy chain (VIF) communication. Do not apply external DC voltage to this pin. Shall connect to COMLN/P of adjacent device through proper isolation, see Section 7.3.2.1.1. Leave unconnected if (Ring Architecture) not used.
COMHP13AC-I/O
COMLN11AC-I/OThis is an AC coupled bi-directional I/O pin for daisy chain (VIF) communication. Do not apply external DC voltage to this pin. Shall connect to COMHN/P of adjacent device through proper isolation, see Section 7.3.2.1.1. Leave unconnected if (Ring Architecture) not used.
COMLP10AC-I/O
INH16HV-OInhibit pin (PMOS open drain) to control system voltage regulators, connect 100kohm resistor to GND. If reverse wake up feature is not used, connect this pin to BAT pin. Don’t leave this pin floating.
BAT15HV-PBattery supply Input. Supply internal LDOs and wakeup circuit. Connect to external supply through 10ohm resistor. Bypass to GND with 0.1μF.
(1) DI = digital input, DO = digital output, HV = high voltage