JAJSP77A November   2019  – August 2020 BQ79600-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 仕様
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Modes and Power Supply
        1. 7.3.1.1 Power Mode
        2. 7.3.1.2 Pings
        3. 7.3.1.3 SPI/UART の選択
        4. 7.3.1.4 Digital Reset
        5. 7.3.1.5 Power Mode in BMS System
        6. 7.3.1.6 Power Supply
        7. 7.3.1.7 Shutdown
      2. 7.3.2 Communication
        1. 7.3.2.1 Data Communication Protocol
          1. 7.3.2.1.1 Frame Layer
            1. 7.3.2.1.1.1 Calculating Frame CRC Value
            2. 7.3.2.1.1.2 Verifying Frame CRC
          2. 7.3.2.1.2 Physical Layer
            1. 7.3.2.1.2.1 UART
              1. 7.3.2.1.2.1.1 TX HOLD OFF
              2. 7.3.2.1.2.1.2 UART COMM CLEAR
            2. 7.3.2.1.2.2 SPI
              1. 7.3.2.1.2.2.1 SPI_RDY と SPI FIFO
              2. 7.3.2.1.2.2.2 Flow to Read/Write BQ79600-Q1
              3. 7.3.2.1.2.2.3 SPI COMM CLEAR
            3. 7.3.2.1.2.3 Daisy Chain
        2. 7.3.2.2 Tone Communication Protocol
        3. 7.3.2.3 Device Auto Addressing / Ring Communication
          1. 7.3.2.3.1 Auto-Addressing
          2. 7.3.2.3.2 Ring Communication (optional)
        4. 7.3.2.4 Communication Timeout
        5. 7.3.2.5 Communication Debug Mode
      3. 7.3.3 Fault Handling
        1. 7.3.3.1 Fault Status Hierarchy/Reset/Mask
          1. 7.3.3.1.1 Fault Status Hierarchy
          2. 7.3.3.1.2 Fault Reset and Mask
        2. 7.3.3.2 Fault Interface
          1. 7.3.3.2.1 NFAULT
          2. 7.3.3.2.2 Daisy Chain (COMH and COML)
            1. 7.3.3.2.2.1 Fault Transmitting when BQ79600-Q1 in ACTIVE
            2. 7.3.3.2.2.2 Fault Transmitting when BQ79600-Q1 in SLEEP
            3. 7.3.3.2.2.3 Fault Transmitting (Automatic Host Wakeup/Reverse Wakeup) when BQ79600-Q1 in SHUTDOWN
      4. 7.3.4 INH/ Reverse Wakeup
      5. 7.3.5 Sniff Detector
      6. 7.3.6 Device Diagnostic
        1. 7.3.6.1 Power Supplies Check
          1. 7.3.6.1.1 Power Supply Diagnostic Check
          2. 7.3.6.1.2 Power Supply BIST
        2. 7.3.6.2 Thermal Shutdown
        3. 7.3.6.3 Oscillators Watchdog
        4. 7.3.6.4 Register Bit Flip Monitor
        5. 7.3.6.5 SPI FIFO 診断
    4. 7.4 Device Functional Modes
    5. 7.5 Register Maps
      1. 7.5.1  Register Summary Table
      2. 7.5.2  Register: DIR0_ADDR
      3. 7.5.3  Register: DIR1_ADDR
      4. 7.5.4  Register: CONTROL1
      5. 7.5.5  Register: CONTROL2
      6. 7.5.6  Register: DIAG_CTRL
      7. 7.5.7  Register: DEV_CONF1
      8. 7.5.8  Register: DEV_CONF2
      9. 7.5.9  Register: TX_HOLD_OFF
      10. 7.5.10 Register: SLP_TIMEOUT
      11. 7.5.11 Register: COMM_TIMEOUT
      12. 7.5.12 Register: SPI_FIFO_UNLOCK
      13. 7.5.13 Register: FAULT_MSK
      14. 7.5.14 Register: FAULT_RST
      15. 7.5.15 Register: FAULT_SUMMARY
      16. 7.5.16 Register: FAULT_REG
      17. 7.5.17 Register: FAULT_SYS
      18. 7.5.18 Register: FAULT_PWR
      19. 7.5.19 Register: FAULT_COMM1
      20. 7.5.20 Register: FAULT_COMM2
      21. 7.5.21 Register: DEV_DIAG_STAT
      22. 7.5.22 Register: PARTID
      23. 7.5.23 Register: DIE_ID1
      24. 7.5.24 Register: DIE_ID2
      25. 7.5.25 Register: DIE_ID3
      26. 7.5.26 Register: DIE_ID4
      27. 7.5.27 Register: DIE_ID5
      28. 7.5.28 Register: DIE_ID6
      29. 7.5.29 Register: DIE_ID7
      30. 7.5.30 Register: DIE_ID8
      31. 7.5.31 Register: DIE_ID9
      32. 7.5.32 Register: DEBUG_CTRL_UNLOCK
      33. 7.5.33 Register: DEBUG_COMM_CTRL
      34. 7.5.34 Register: DEBUG_COMM_STAT
      35. 7.5.35 Register: DEBUG_SPI_PHY
      36. 7.5.36 Register: DEBUG_SPI_FRAME
      37. 7.5.37 Register: DEBUG_UART_FRAME
      38. 7.5.38 Register: DEBUG_COMH_PHY
      39. 7.5.39 Register: DEBUG_COMH_FRAME
      40. 7.5.40 Register: DEBUG_COML_PHY
      41. 7.5.41 Register: DEBUG_COML_FRAME
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Bridge With Reverse Wakeup in UART
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 MCU Interface (UART, NFAULT)
          2. 8.2.1.2.2 Daisy Chain Interface
          3. 8.2.1.2.3 INH Connection
        3. 8.2.1.3 Application Performance Plot
      2. 8.2.2 Bridge Without Reverse Wakeup in SPI
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 MCU Interface (SPI, SPI_RDY, NFAULT)
          2. 8.2.2.2.2 Daisy Chain Interface
        3. 8.2.2.3 Application Performance Plot
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground Planes
      2. 10.1.2 Bypass Capacitors for Power Supplies
      3. 10.1.3 UART/SPI communication
      4. 10.1.4 Daisy Chain Communication
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER STATE TIMING
tPOR2COMM From VBAT (rising) > VPOR to device ready to receive WAKE ping, ramp up VBAT and VIO in 10µs 1 ms
tSU(WAKE_SHUT) Startup from SHUTDOWN/VALIDATE to ACTIVE mode From receiving WAKE ping (RX ping going low-to-high) to device in ACTIVE mode (ready to do µART /SPI communication) (CVDD= 0.22µF capacitor DVDD = 0.22µF capacitor) 2 3.5 ms
tSU(SLP2ACT) Startup from SLEEP to ACTIVE mode (with Sleep2active ping) From receiving SLP2ACT ping (RX ping going low-to-high) to device in ACTIVE mode (ready to do UART /SPIcommunication) 260 µs
tSU(WAKE_SLP) Startup from SLEEP to ACTIVE mode (with WAKE ping) From receiving WAKE ping (RX ping going low-to-high) to device in ACTIVE mode (ready to do UART /SPIcommunication) 600 µs
tRST Reset time from ACTIVE mode to ACTIVE mode From receiving WAKE ping (RX ping going low-to-high) or CONTROL1[SOFT_RESET]=1 to device in ACTIVE mode (ready to do UART /SPI communication) 600 µs
tSLP From ACTIVE to SLEEP mode From receiving SLEEP entry condition to enter in SLEEP mode 100 µs
tSHTDN From ACTIVE/SLEEP/VALIDATE to SHUTDOWN mode From receiving SHUTDOWN entry condition to enter in SHUTDOWN mode (CVDD<1.2V) 5 ms
tVALID_ENTRY From SHUTDOWN to VALIDATE From fault tone toggling on COM port to DVDD hit above 1.75V 10 ms
tVALID_TIMEOUT time to validate fault tone before transition to SHUTDOWN state Start from DVDD out of reset 150 ms
INH Driver TIMING
tINH_DLY After device enters VALIDATE, from first couplet of fault tone to INH pulled high 720 µs
PING SIGNAL TIMING
tHLD_WAKE From user perspective, WAKE ping low time on MOSI/RX pin VBAT > VPOR, RX pin (low-pulse width) VIO = 3.3 or 5V 2.5 3 ms
tHLD_SD From user perspective, SHUTDOWN ping low time on MOSI/RX pin VBAT > VPOR, RX pin (low-pulse width) VIO = 3.3 or 5V 12.5 ms
tStA From user perspective, SLEEPtoACTIVE ping low time on MOSI/RX pin VBAT > VPOR 250 300 µs
Daisy-chain Communication Bus TIMING
tPW_DC COMM data Pulse width of data (half bit time) for communiction 230 250 270 ns
tCOMTONE Time between pulses within a comm tone (HFO based). Transmit. From the beginning of a pulse until the beginning of the next pulse. 10.67 11 11.33 µs
tCOMTONE_PLS Comm tone pulse width(HFO based) Transmit 0.97 1 1.03 µs
tFLTTONE Time between pulses within a fault tone (LFO based). Only transmit HB tone, not FAULT tone. From the beginning of a pulse until the beginning of the next pulse.  10.3 11.5 12.7 µs
tFLTTONE_PLS Fault tone or HB tone pulse width (analog delay based) 1 µs
nHBDET HEARTBEAT: Number of pulses to detect as a valid tone (dig counter) Detect 16 pulses
nFTONEDET FAULT TONE: Number of pulses to detect as a valid tone  (dig counter) Detect 64 pulses
tHB_PERIOD HEARTBEAT: Period between HEARTBEAT Burst (from the beginning of a HEARTBEAT to the beginning of the next HEARTBEAT) 360 400 440 ms
tHB_TIMEOUT HEARTBEAT: Timeout to considered as not receving HEARTBEAT 0.9 1 1.1 s
tHB_FAST HEARTBEAT: If HEARTBEAT is received within this time, it is considered receving HEARTBEAT too fast 200 ms
tFTONE_PERIOD Defined by BQ7961X, FAULT TONE: Period between FAULT TONE Burst From the beginning of a FAULT TONE to the beginning of the next FAULT TONE 50 ms
tFT_LATENCY Fault Tone latency in Base Device From the time device receives the tone to the time asserts NFAULT 24 µs
I/O TIMING (TX, RX, NFAULT)
tRISE_TX Rise Time CLOAD = 100pF, VIO=3.3V or 5V 15 ns
tFALL_TX Fall Time CLOAD = 100pF, VIO=3.3V or 5V 15 ns
tFALL/RISE_RX RX pin rise/fall time 100 ns
UART TIMING
UARTERR_BAUD UART TX/RX baud rate (either 250K or 1Mbps) error –1.5 1.5 %
tUART(CLR) UART Comm Clear low time 15 20 bit period
tUART(RX_HIGH) UART high time after Comm Clear, before sending Clear or Reset 1 bit period
SPI TIMING
SCLK SPI clock freq 2 6 MHz
nSPI(CLR) SPI Comm Clear low time 8 bit
tSPI_R SPI clock rising edge 25% to 75% 10 ns
tSPI_F SPI clock falling edge 25% to 75% 10 ns
tSPI_CLKH SPI clock high time 70 ns
tSPI_CLKL SPI clock low time 70 ns
t8 Max SPI_RDY service interval. This time doesn't apply if total response bytes (payload + overhead) is less than 256 bytes  Read SCLK = 6MHz, with 30% SPI BUS idle time 1 ms
t9 From nCS (25%) to SCLK rising (75%) 500 ns
t10 From SCLK falling (25%) to nCS (75%) 500 ns
t11 From nCS rising(75%) to nCS falling(25%) Don't drop nCS while SPI_RDY is low 1 µs
t12 From nCS falling (25%) to stable MISO(L:20% H:80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns
t13 From SCLK falling (25%) to stable MISO(L:20% H:80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns
t14 From nCS rising (75%) to MISO drive to  '1' (80%) Timing is defined at device pins, exclude propergation delay of PCB traces (from device perspective) 42 ns
tSU Setup time, refer to 75% of SCLK rising 20 ns
tH Hold time, refer to 75% of SCLK rising 20 ns
SNIFF DETECTOR
nVALIDATE Number of pulses needed (digital counter) to transition to validate mode Sniffer is enabled, and device is in SHUTDOWN mode 64 pulses
tSNIFFIDLE Timer length. Once timer expired, it resets the 64 counter Sniffer is enabled, and device is in SHUTDOWN mode 20 52 µs
OSCILLATOR
fHFO HFO frequency 31.52 32 32.48 MHz
tHFOWDG HFO watchdog time Reset digital if HFO is stuck or period is > than the watchdog timer 35 µs
fLFO LFO frequency 235.8 262 288.2 kHz
tLFOWDG LFO watchdog time Reset digital if LFO is stuck or period is > than the watchdog timer 35 µs