JAJSP77A November 2019 – August 2020 BQ79600-Q1
PRODUCTION DATA
This bit flip checker monitors 2 configuration registers: DEV_CONF1, FAULT_MSK. It is always running when device is out of SHUTDOWN. Whenever user changes those 2 register settings or any of the register bit flips, fault bit [CONF_MON_ERR] is set.
Once user changes the setting, user shall write [CONF_MON_GO]=1 (resample 2 register values), write [RST_REG] =1 to clear the [CONF_MON_ERR] fault, after this point, if any bit flips among those 2 registers, [CONF_MON_ERR] is set. After device resets (receive WAKE ping or [SOFT_RESET] = 1), [CONF_MON_ERR] = 0.
This device does not have customer register CRC check and the register bit flip monitor provides the protection for the above mentioned customer registers.