JAJSHI5G august   2012  – april 2023 DLP7000

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Storage Conditions
    3. 7.3  ESD Ratings
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Thermal Information
    6. 7.6  Electrical Characteristics
    7. 7.7  LVDS Timing Requirements
    8. 7.8  LVDS Waveform Requirements
    9. 7.9  Serial Control Bus Timing Requirements
    10. 7.10 Systems Mounting Interface Loads
    11. 7.11 Micromirror Array Physical Characteristics
    12. 7.12 Micromirror Array Optical Characteristics
    13. 7.13 Window Characteristics
    14. 7.14 Chipset Component Usage Specification
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DLPC410 Chipset DMD Features
        1. 8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset
        2. 8.3.1.2 DLPA200 - DMD Micromirror Driver
        3. 8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset
        4. 8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD
          1. 8.3.1.4.1 DLP7000 XGA Chip Set Interfaces
            1. 8.3.1.4.1.1 DLPC410 Interface Description
              1. 8.3.1.4.1.1.1 DLPC410 IO
              2. 8.3.1.4.1.1.2 Initialization
              3. 8.3.1.4.1.1.3 DMD Device Detection
              4. 8.3.1.4.1.1.4 Power Down
          2. 8.3.1.4.2 DLPC410 to DMD Interface
            1. 8.3.1.4.2.1 DLPC410 to DMD IO Description
            2. 8.3.1.4.2.2 Data Flow
          3. 8.3.1.4.3 DLPC410 to DLPA200 Interface
            1. 8.3.1.4.3.1 DLPA200 Operation
            2. 8.3.1.4.3.2 DLPC410 to DLPA200 IO Description
          4. 8.3.1.4.4 DLPA200 to DLP7000 Interface
            1. 8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview
        5. 8.3.1.5 Measurement Conditions
    4. 8.4 Device Functional Modes
      1. 8.4.1 DMD Operation
        1. 8.4.1.1 Single Block Mode
        2. 8.4.1.2 Dual Block Mode
        3. 8.4.1.3 Quad Block Mode
        4. 8.4.1.4 Global Mode
    5. 8.5 Optical Interface and System Image Quality Considerations
      1. 8.5.1 Optical Interface and System Image Quality
      2. 8.5.2 Numerical Aperture and Stray Light Control
      3. 8.5.3 Pupil Match
      4. 8.5.4 Illumination Overfill
    6. 8.6 Micromirror Array Temperature Calculation
      1. 8.6.1 Package Thermal Resistance
      2. 8.6.2 Case Temperature
      3. 8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display applications)
      4. 8.6.4 Micromirror Array Temperature Calculation - Power Density Based
      5. 8.6.5 62
    7. 8.7 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 8.7.2 Landed Duty Cycle and Useful Life of the DMD
      3. 8.7.3 Landed Duty Cycle and Operational DMD Temperature
      4. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Device Description
      3. 9.2.3 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 DMD Power-Up and Power-Down Procedures
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Impedance Requirements
      2. 11.1.2 PCB Signal Routing
      3. 11.1.3 DMD Interface
        1. 11.1.3.1 Trace Length Matching
      4. 11.1.4 DLP7000 Decoupling
        1. 11.1.4.1 Decoupling Capacitors
      5. 11.1.5 VCC and VCC2
      6. 11.1.6 DMD Layout
      7. 11.1.7 DLPA200
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1  Device Support
      1. 12.1.1 Device Marking
    2. 12.2  サード・パーティ製品に関する免責事項
    3. 12.3  Documentation Support
      1. 12.3.1 Related Documents
    4. 12.4  ドキュメントの更新通知を受け取る方法
    5. 12.5  サポート・リソース
    6. 12.6  静電気放電に関する注意事項
    7. 12.7  Export Control Notice
    8. 12.8  用語集
    9. 12.9  Related Links
    10. 12.10 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MINMAXUNIT
ELECTRICAL
VCCVoltage applied to VCC (2)(3)–0.54V
VCCIVoltage applied to VCCI (2)(3)–0.54V
VCC2Voltage applied to VVCC2 (2)(3) (4)–0.58V
VMBRSTMicromirror Clocking Pulse Waveform Voltage applied to MBRST[15:0] Input Pins (supplied by DLPA200)–2828V
|VCC – VCCI|Supply voltage delta (absolute value) (4)0.3V
Voltage applied to all other input pins(2)–0.5VCC + 0.3V
|VID|Maximum differential voltage, damage can occur to internal termination resistor if exceeded, see LVDS Waveform Requirements700mV
IOHCurrent required from a high-level outputVOH = 2.4 V–20mA
IOLCurrent required from a low-level outputVOL = 0.4 V15mA
ENVIRONMENTAL
TARRAYArray temperature: operational(5)1065°C
Array temperature: non-operational(5)–4080°C
TDELTAAbsolute temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1(6)10°C
RHOperating relative humidity (non-condensing)095%
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS (ground).
(3) VOFFSET supply transients must fall within specified max voltages.
(4) To prevent excess current, the supply voltage delta |VCC – VCCI| must be less than specified limit.
(5) DMD Temperature is the worst-case of any test point shown in Thermal Test Point Location, or the active array as calculated by the Micromirror Array Temperature Calculation.
(6) As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation.