JAJSHI5G august 2012 – april 2023 DLP7000
PRODUCTION DATA
Figure 8-1 is a simplified system block diagram showing the use of the following components:
● | DLPC410 | – | Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200 timing and control |
● | DLPR410 | – | [XCF16PFSG48C] serial flash PROM contains startup configuration information (EEPROM) |
● | DLPA200 | – | DMD micromirror driver for the DLP7000 DMD |
● | DLP7000 | – | Spatial Light Modulator (DMD) |