JAJSM07C November 2019 – March 2022 LMX2694-SEP
PRODUCTION DATA
R70 is shown in Figure 7-80 and described in Table 7-90.
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASH_RST_COUNT[15:0] | |||||||||||||||
R/W-0xC350 | |||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-0 | MASH_RST_COUNT[15:0] | R/W | 0xC350 | Lower 16 bits of MASH_RST_COUNT. This register is used to add a delay when using phase SYNC. The delay should be set at least four times the PLL lock time. This delay is expressed in state machine clock periods. One of these periods is equal to 2CAL_CLK_DIV / fOSC. |