JAJSOV9A March   2023  – December 2023 TMAG5170D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Magnetic Characteristics
    7. 5.7 Power up Timing
    8. 5.8 SPI Interface Timing
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Magnetic Flux Direction
      2. 6.3.2 Sensor Location
      3. 6.3.3 Magnetic Range Selection
      4. 6.3.4 Update Rate Settings
      5. 6.3.5 ALERT Function
        1. 6.3.5.1 Interrupt and Trigger Mode
        2. 6.3.5.2 Magnetic Switch Mode
      6. 6.3.6 Threshold Count
      7. 6.3.7 Diagnostics
        1. 6.3.7.1  Memory Cyclic Redundancy Check (CRC)
        2. 6.3.7.2  ALERT Integrity Check
        3. 6.3.7.3  VCC Check
        4. 6.3.7.4  Internal LDO Undervoltage Check
        5. 6.3.7.5  Digital Core Power-On Reset Check
        6. 6.3.7.6  SDO Output Check
        7. 6.3.7.7  Communication Cyclic Redundancy Check (CRC)
        8. 6.3.7.8  Oscillator Integrity Check
        9. 6.3.7.9  Magnetic Field Threshold Check
        10. 6.3.7.10 Temperature Alert Check
        11. 6.3.7.11 Analog Front-End (AFE) Check
        12. 6.3.7.12 Hall Resistance and Switch Matrix Check
        13. 6.3.7.13 Hall Offset Check
        14. 6.3.7.14 ADC Check
    4. 6.4 Device Functional Modes
      1. 6.4.1 Operating Modes
        1. 6.4.1.1 Active Mode
        2. 6.4.1.2 Standby Mode
        3. 6.4.1.3 Configuration Mode (DEFAULT)
        4. 6.4.1.4 Sleep Mode
        5. 6.4.1.5 Wake-Up and Sleep Mode
        6. 6.4.1.6 Deep-Sleep Mode
    5. 6.5 Programming
      1. 6.5.1 Data Definition
        1. 6.5.1.1 Magnetic Sensor Data
        2. 6.5.1.2 Temperature Sensor Data
        3. 6.5.1.3 Magnetic Sensor Offset Correction
        4. 6.5.1.4 Angle and Magnitude Data Definition
      2. 6.5.2 Serial Peripheral Interface (SPI)
        1. 6.5.2.1 SCK
        2. 6.5.2.2 CS
        3. 6.5.2.3 SDI
        4. 6.5.2.4 SDO
          1. 6.5.2.4.1 Regular 32-Bit SDO Read
          2. 6.5.2.4.2 Special 32-Bit SDO Read
        5. 6.5.2.5 SPI CRC
        6. 6.5.2.6 SPI Frame
          1. 6.5.2.6.1 32-Bit Read Frame
          2. 6.5.2.6.2 32-Bit Write Frame
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Selecting the Sensitivity Option
      2. 7.1.2 Temperature Compensation for Magnets
      3. 7.1.3 Sensor Conversion
        1. 7.1.3.1 Continuous Conversion
        2. 7.1.3.2 Trigger Conversion
        3. 7.1.3.3 Pseudo-Simultaneous Sampling
      4. 7.1.4 Error Calculation During Linear Measurement
      5. 7.1.5 Error Calculation During Angular Measurement
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
        1. 7.2.1.1 Gain Adjustment for Angle Measurement
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Register Map
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
6.5.2.4.2 Special 32-Bit SDO Read

With DATA_TYPE > 000b, the TMAG5170D-Q1 supports a special 32-bit SDO frame for two-channel simultaneous data read. Each channel data is limited to 12 bits. This feature is useful for systems requiring faster data throughput while performing multi-axis measurements. Figure 6-8 explains the detail construction of the special 32-bit SDO frame. When the device is set to special 32-bit read, the device will continue to deliver the 2-channel data set through the SDO line during consecutive read or write cycles. DATA_TYPE bits must be reset to get back to a regular read cycle. Only four status bits are transmitted in this mode. All the status bits except for the ERROR_STAT bit are directly read from the status registers. The ERROR_STAT bit indicates if any error bit set in the device. The status bits, STAT[2:0], can be changed based off CMD1 value in the previous frame.


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Figure 6-8 Special 32-Bit SDO Read