JAJSHQ8D July   2019  – July 2021 TPS25832-Q1 , TPS25833-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Switching Characteristics
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
    1.     18
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1  Buck Regulator
      2. 10.3.2  Enable/UVLO and Start-up
      3. 10.3.3  RT/SYNC
      4. 10.3.4  Spread-Spectrum Operation
      5. 10.3.5  VCC, VCC_UVLO
      6. 10.3.6  Minimum ON-time, Minimum OFF-time
      7. 10.3.7  Internal Compensation
      8. 10.3.8  Bootstrap Voltage (BOOT)
      9. 10.3.9  RSNS, RSET, RILIMIT, and RIMON
      10. 10.3.10 Overcurrent and Short Circuit Protection
        1. 10.3.10.1 Current Limit Setting using RILIMIT
        2. 10.3.10.2 Buck Average Current Limit Design Example
        3. 10.3.10.3 External MOSFET Gate Drivers
        4. 10.3.10.4 Cycle-by-Cycle Buck Current Limit
      11. 10.3.11 IEC and Overvoltage Protection
        1. 10.3.11.1 VBUS and VCSN/OUT Overvoltage Protection
        2. 10.3.11.2 DP_IN and DM_IN Protection
        3. 10.3.11.3 CC IEC and Overvoltage Protection
      12. 10.3.12 Cable Compensation
        1. 10.3.12.1 Cable Compensation Design Example
      13. 10.3.13 USB Port Control
      14. 10.3.14 FAULT Response
      15. 10.3.15 USB Specification Overview
      16. 10.3.16 USB Type-C® Basics
        1. 10.3.16.1 Configuration Channel
        2. 10.3.16.2 Detecting a Connection
        3. 10.3.16.3 Configuration Channel Pins CC1 and CC2
        4. 10.3.16.4 Current Capability Advertisement and VCONN Overload Protection
        5. 10.3.16.5 Plug Polarity Detection
      17. 10.3.17 Device Power Pins (IN, CSN/OUT, and PGND)
      18. 10.3.18 Thermal Shutdown
      19. 10.3.19 Power Wake
      20. 10.3.20 Thermal Sensing with NTC (TPS25833-Q1)
    4. 10.4 Device Functional Modes
      1. 10.4.1 Shutdown Mode
      2. 10.4.2 Standby Mode
      3. 10.4.3 Active Mode
      4. 10.4.4 Device Truth Table (TT)
      5. 10.4.5 USB Port Operating Modes
        1. 10.4.5.1 USB Type-C® Mode
        2. 10.4.5.2 Standard Downstream Port (SDP) Mode — USB 2.0, USB 3.0, and USB 3.1
        3. 10.4.5.3 Charging Downstream Port (CDP) Mode
        4. 10.4.5.4 Dedicated Charging Port (DCP) Mode (TPS25833-Q1 Only)
          1. 10.4.5.4.1 DCP BC1.2 and YD/T 1591-2009
          2. 10.4.5.4.2 DCP Divider-Charging Scheme
          3. 10.4.5.4.3 DCP 1.2-V Charging Scheme
        5. 10.4.5.5 DCP Auto Mode (TPS25833-Q1 Only)
      6. 10.4.6 High-Bandwidth Data-Line Switches (TPS25832-Q1 Only)
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1  Output Voltage
        2. 11.2.2.2  Switching Frequency
        3. 11.2.2.3  Inductor Selection
        4. 11.2.2.4  Output Capacitor Selection
        5. 11.2.2.5  Input Capacitor Selection
        6. 11.2.2.6  Bootstrap Capacitor Selection
        7. 11.2.2.7  VCC Capacitor Selection
        8. 11.2.2.8  Enable and Under Voltage Lockout Set-Point
        9. 11.2.2.9  Current Limit Set-Point
        10. 11.2.2.10 Cable Compensation Set-Point
        11. 11.2.2.11 LD_DET, POL, and FAULT Resistor Selection
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Ground Plane and Thermal Considerations
    3. 13.3 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 サポート・リソース
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

GUID-7DF787B8-56D2-4E47-B1DB-DA98B43E2CCB-low.gifFigure 7-1 TPS25832QWRHBRQ1 Package32-Pin (VQFN)Top View
GUID-20210719-CA0I-7CLS-VBPV-HJR0DL18JMHT-low.gifFigure 7-3 TPS25832QCWRHBRQ1 Package32-Pin (VQFN)Top View
GUID-A921DCE6-4824-4B8E-9BC1-B6DF8C2E9480-low.gifFigure 7-2 TPS25833QWRHBRQ1 Package32-Pin (VQFN)Top View
GUID-20210719-CA0I-ZMDV-LD7C-9B23W7ZBZLD6-low.gifFigure 7-4 TPS25833QCWRHBRQ1 Package32-Pin (VQFN)Top View
Table 7-1 Pin Functions
NAME 832-Q1
NO.		 833-Q1
NO.		 TYPE (1) I/O DESCRIPTION
AGND 16 16 G – Analog ground terminal. Ground reference for internal references and logic. All electrical parameters are measured with respect to this pin. Connect to system ground on PCB.
BOOT 32 32 P Boot-strap capacitor connection for HS FET driver. Connect a high quality 100-nF capacitor from this pin to the SW pin.
BUS 15 15 A I VBUS discharge input. Connect to VBUS on USB Connector.
CC1 20 20 A I/O Analog input/output. Connect to Type-C CC1 pin.
CC2 19 19 A I/O Analog input/output. Connect to Type-C CC2 pin.
CSN/OUT 13 13 A I Negative input of current sense amplifier, also buck output for internal voltage regulation.
CSP 14 14 A I Positive input of current sense amplifier.
CTRL1 5 5 A I Logic-level control inputs for device/system configuration (see Table 10-10).
CTRL2 6 6 A I Logic-level control inputs for device/system configuration (see Table 10-10).
DM_IN 17 17 A DM data line. Connect to USB connector.
DM_OUT 8 – A DM data line. Connect to USB host controller.
DP_IN 18 18 A DP data line. Connect to USB connector.
DP_OUT 7 – A DP data line. Connect to USB host controller.
EN/UVLO 4 4 A Enable pin. Do not float. High = on, Low = off. Can be tied to VIN. Precision enable input allows adjustable UVLO by external resistor divider.
FAULT 24 24 A O Active LOW open-drain output. Asserted during fault conditions (see Table 10-4).
ILIMIT 12 12 A External resistor used to set the current-limit threshold (see Table 10-2).
IMON 11 11 A External resistor used to set the max cable comp voltage at full load current.
IN 1, 2, 3 1, 2, 3 P I Input Supply to regulator. Connect a high-quality bypass capacitor(s) directly to this pin and PGND.
LD_DET 23 23 A O Active LOW open-drain output. Asserted when a Type-C UFP is identified on the CC lines.
LS_GD 10 10 A External NMOS gate driver. For TPS25832-Q1, LS_GD pin must be pulled up through a 2.2-kΩ resistor under average current limit mode.(see Current Limit Setting using RILIMIT).
NTC – 8 I Input for negative temperature coefficient resistor divider. Use to monitor external PCB temperature (see Thermal Sensing with NTC (TPS25833-Q1)).
PGND 25, 26, 27 25, 26, 27 G – Power ground terminal. Connect to system ground and AGND. Connect to bypass capacitor with short wide traces.
POL 22 22 A O Active LOW open-drain output. Signals which Type-C CC pin is connected to the CC line. This gives cable orientation information needed to mux the super speed lines. Asserted when the CC2 pin is connected to the CC line in the cable.
RT/SYNC 9 9 A Resistor Timing or External Clock input. An internal amplifier holds this terminal at a fixed voltage when using an external resistor to ground to set the switching frequency. If the terminal is pulled above the PLL upper threshold, a mode change occurs and the terminal becomes a synchronization input. The internal amplifier is disabled and the terminal is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the operating mode returns to resistor frequency programming.
SW 28, 29, 30, 31 28, 29, 30, 31 P Switching output of the regulator. Internally connected to source of the HS FET and drain of the LS FET. Connect to power inductor.
THERM_WARN – 7 A O Active LOW open-drain output. Asserted when voltage at the NTC pin increases above the thermal warning threshold.
VCC 21 21 P Output of internal bias supply. Used as supply to internal control circuits. Connect a high quality 2.2-µF capacitor from this pin to GND.
(1) A = Analog, P = Power, G = Ground.