JAJSIN7 February   2020 TPS59632-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Current Sensing
      3. 7.3.3  Load-line (Droop)
      4. 7.3.4  Load Transients
      5. 7.3.5  Overshoot Reduction (OSR)
      6. 7.3.6  Undershoot Reduction (USR)
      7. 7.3.7  Autobalance Current Sharing
      8. 7.3.8  PWM And SKIP Signals
      9. 7.3.9  Bias Power (V5A, VDD, And VINTF) UVLO
      10. 7.3.10 Start-Up Sequence
      11. 7.3.11 Power Good Operation
      12. 7.3.12 Analog Current Monitor, IMON, And Corresponding Digital Output Current
      13. 7.3.13 Fault Behavior
      14. 7.3.14 Output Under Voltage Protection (UVP)
      15. 7.3.15 Output Over Voltage Protection (OVP)
      16. 7.3.16 Over Current Protection (OCP)
      17. 7.3.17 Over Current Warning
      18. 7.3.18 Input Voltage Limits
      19. 7.3.19 VID Table
    4. 7.4 User Selections
    5. 7.5 I2C Interface Operation
      1. 7.5.1 Key For Protocol Examples
      2. 7.5.2 Protocol Examples
    6. 7.6 I2C Register Maps
      1. 7.6.1 Voltage Select Register (VSR) (Address = 00h)
      2. 7.6.2 IMON Register (Address = 03h)
      3. 7.6.3 VMAX Register (Address = 04h)
      4. 7.6.4 Power State Register (Address = 06h)
      5. 7.6.5 Slew Register (Address = 07h)
      6. 7.6.6 Lot Code Registers (Address = 10-13h)
      7. 7.6.7 Fault Register (Address = 14h)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 3-Phase D-CAP+™, Step-Down Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Step 1: Select Switching Frequency
          2. 8.2.1.2.2  Step 2: Set The Slew Rate
          3. 8.2.1.2.3  Step 3: Set The I2C Address
          4. 8.2.1.2.4  Step 4: Determine Inductor Value And Choose Inductor
          5. 8.2.1.2.5  Step 5: Current Sensing Resistance
          6. 8.2.1.2.6  Step 6: Select Over Current Protection (OCP) Setting
          7. 8.2.1.2.7  Step 7: Current Monitor (IMON) Setting
          8. 8.2.1.2.8  Step 8: Set the Load-Line Slope
          9. 8.2.1.2.9  Step 9: Voltage Feedback Resistor Calculation
          10. 8.2.1.2.10 Step 10: Ramp Compensation Selection
          11. 8.2.1.2.11 Step 11 Overshoot Reduction (OSR) selection
          12. 8.2.1.2.12 Step 12: Undershoot Reduction (USR) selection
          13. 8.2.1.2.13 Step 13: Loop Compensation
        3. 8.2.1.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1  Layout Guidelines
    2. 10.2  Layout Example
    3. 10.3  Current Sensing Lines
    4. 10.4  Feedback Voltage Sensing Lines
    5. 10.5  PWM And SKIP Lines
    6. 10.6  Power Chain Symmetry
    7. 10.7  Component Location
    8. 10.8  Grounding Recommendations
    9. 10.9  Decoupling Recommendations
    10. 10.10 Conductor Widths
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape And Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Switching Characteristics

Over recommended temperature range, 4.5 V ≤ VV5A ≤ 5.5 V, 3.0 V ≤ VVDD ≤ 3.6 V, VGFB = GND, VVFB = VCORE (unless otherwise noted).
PARAMETER CONDITIONS MIN TYP MAX UNIT
TIMERS: START-UP, PWM ON-TIME AND I/O TIMING
tSTART-CB Cold boot time VBOOT > 0V , EN = high, time from UVLO to VOUT ramp, CREF = 0.33 µF 1.2 ms
tSTBY-E STBY exit time Time from EN assertion until PGOOD goes high. VVID = 1.28 V, RSLEW = 39 kΩ 250 µs
tPGDDGLTO PGOOD deglitch time Time from VFB out of 250 mV VDAC boundary to PGOOD low. 1 µs
tPGDDGLTU PGOOD deglitch time Time from VFB out of –300 mV VDAC boundary to PGOOD low. 31
tON PWM ON-time RF = 24 kΩ, VBAT = 12 V, VVFB = 1 V (400 kHz) 230 ns
RF = 39 kΩ, VBAT = 12 V, VVFB = 1 V (600 kHz) 164
RF = 75 kΩ, VBAT = 12 V, VVFB = 1 V (800 kHz) 140
RF = 150 kΩ, VBAT = 12 V, VVFB = 1 V (1 MHz) 122
tOFF_MIN Controller minimum OFF time Fixed value 20 ns
tON_MIN Controller minimum ON time RCF = 150 kΩ, VBAT = 20 V, VVFB = 0 V 20
tVCCVID VID change to VFB change(1) ACK of VID change command to start of voltage ramp 1 µs
tPG2 PGOOD low after enable goes low Low-state time after EN goes low. 225 250 275 µs
PWM OUTPUTS: I/O VOLTAGE AND CURRENT
tP-S_H-L PWMx H-L transition time 10 to 90%, both edges 7 20 ns
tP-S_TRI PWMx 3-state transition 10 or 90% to 3-state level, both edges 5 20