JAJSNJ1H May 2013 – December 2021 TPS65310A-Q1
PRODUCTION DATA
The SPI provides a communication channel between the TPS65310A-Q1 device and a controller. The TPS65310A-Q1 device is always the peripheral. The processor/MCU is always the controller . The SPI controller selects the TPS65310A-Q1 device by setting CSN (chip select) to low. SDI (peripheral in) is the data input, SDO (peripheral out) is the data output, and SCK (serial clock input) is the SPI clock provided by the controller. If chip select is not active (high), the data output SDO is high impedance. Each communication consist of 16 bits.
1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])
1 bit R/W; read = 0 and write = 1
6 bits CMD identifier
8 bits data
Each command is valid if:
The response to each controller command is given in the following SPI cycle. The response address is the CMD_ID of the previous sent message and the corresponding data byte. The response data is latched with the previous cycle such that a response to a write command is the status of the register before the write access. (Same response as a read access.) The response to an invalid command is the original command with the correct parity bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication (CMD_ID = 0x03). Write access to a read-only register is not reported as an SPI error and is treated as a read access. The initial answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.