SBVS336A September 2021 – May 2022 TPS7A94
The device is designed to be stable using low equivalent series resistance (ESR) and low equivalent series inductance (ESL) ceramic capacitors at the input, output, and noise-reduction pin. Multilayer ceramic capacitors have become the industry standard for these applications and are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-rated, or better dielectric materials provide relatively good capacitive stability across temperature. The use of Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and temperature. The input and output capacitors recommended herein account for a capacitance derating of approximately 50%, but at high VIN and VOUT conditions (VIN = 5.5 V to VOUT = 5.0 V), the derating can be greater than 50%, which must be taken into consideration.
The device requires input, output, and noise-reduction capacitors for proper operation of the LDO. Use the nominal or larger than the nominal input, and output capacitors as specified in the Section 6.3 table. Place input and output capacitors as close as possible to the corresponding pin and make the capacitor GND connections as close as possible to the device GND pin to minimize PCB loop inductance, thus reducing transient voltage spikes during a load step.
As illustrated in Figure 8-14, multiple parallel capacitors can be used to lower the impedance present on the line. This capacitor counteracts input trace inductance, improves transient response, and reduces input ripple and noise. Using an output capacitor larger than the typical value can also improve the transient response.