JAJSEQ5A August   2017  – February 2018 UCC24612

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ハイサイドSRによるフライバック
      2.      ローサイドSRによるフライバック
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Management
      2. 7.3.2 Synchronous Rectifier Control
      3. 7.3.3 Adaptive Blanking Time
        1. 7.3.3.1 Turn-On Blanking Timer (Minimum On Time)
        2. 7.3.3.2 Turn-Off Blanking Timer
        3. 7.3.3.3 SR Turn-on Re-arm
      4. 7.3.4 Gate Voltage Clamping
      5. 7.3.5 Standby Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 UVLO Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Run Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 SR MOSFET Selection
        2. 8.2.2.2 Bypass Capacitor Selection
        3. 8.2.2.3 Snubber design
        4. 8.2.2.4 High-Side Operation
      3. 8.2.3 Application Curves
        1. 8.2.3.1 Steady State Testing Low-Side Configuration
        2. 8.2.3.2 Steady State Testing High-Side Configuration
  9. Power Supply Recommendations
  10. 10PCB Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 コミュニティ・リソース
    2. 11.2 商標
    3. 11.3 静電気放電に関する注意事項
    4. 11.4 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Snubber design

It is required for the user to setup snubber components C3 and R3 to get the best performance when using the UCC24612EVM.

To setup these components will require knowledge of the Flyback transformer secondary leakage inductance (Lslk) and measuring the secondary resonant ring frequency (fr) in circuit. It is recommended that the SR is not driven while doing this to simplify the process. It is also recommended to do this test at partial load to avoid creating too much heat on the SR body diode because the conduction loss is much higher. TP3 should be disconnected from the Flyback converter to ensure FET Q1 is turned off while setting up the snubber.

The secondary winding capacitance (Cs) then needs to be calculated based on the following equation. Please note for a transformer with a secondary winding leakage inductance of 3.8 µH and a ring frequency of 2 MHz, the parasitic capacitance would be 1.7 nF, for example.

Equation 3. UCC24612 Equ1.gif

Based on the calculated Cs, Lslk and fr, the snubber resistor R3 can be set to critically dampen the ringing on the secondary, which requires setting the Q of the circuit equal to 1.

Equation 4. UCC24612 Eq2.gif

Capacitor C3 is used to limit the time the snubber resistor is applied to the aux winding during the switching cycle. It is recommended to set the snubber capacitor C3 with the following equation based on the Flyback converters switching frequency (fSW). For a Flyback converter switching at 85 kHz in the example would require a C3 of roughly 497 pF.

Equation 5. UCC24612 Eq3.gif

Please note that the calculations for R3 and C3 are just starting points and should be adjusted based on individual preference, performance and efficiency requirements. More snubber design information can be found in "Snubber Circuits Theory, Design and Application".