SBAA461 December   2020 ADC3541 , ADC3542 , ADC3543 , ADC3544 , ADC3641 , ADC3642 , ADC3643 , ADC3644 , ADC3660 , ADC3681 , ADC3682 , ADC3683

 

  1.   Trademarks
  2. 1Introduction
  3. 2Reduce Data Rates: Optimize Pin Count and Data Rate
    1. 2.1 Parallel CMOS
      1. 2.1.1 Parallel SDR
      2. 2.1.2 Parallel DDR
    2. 2.2 Serial CMOS
      1. 2.2.1 2 Wire
      2. 2.2.2 1 Wire
      3. 2.2.3 0.5 Wire
  4. 3Reduce Data Rates: Decimation
  5. 4Summary
  6. 5References

2 Reduce Data Rates: Optimize Pin Count and Data Rate

The CMOS interface is very common for high-speed data converters, and we typically see a maximum rate of 250 Mbps for CMOS interface. While the ADC36XX family also offers LVDS output data (see ADC3683 and ADC3663), this section focuses primarily on the CMOS interface of the ADC3643 and ADC3541, and trade-offs to consider when optimizing your application.

The ADC3643 and ADC3541 can be configured in a parallel or serial CMOS mode. Both of these modes have unique features, so it is important to understand both accordingly.