SBOA508 January   2022 INA818 , INA819 , INA823 , INA849 , OPA2392 , OPA391 , OPA392 , OPA396 , OPA397 , OPA3S328

 

  1.   Trademarks
  2. 1Single N-FET or P-FET vs Complimentary N-P-FET Input Stage Limitations
  3. 2Example 1: Output Swing Limitation from VCM in an Op-Amp for Low Side Current Sense
  4. 3Bipolar and CMOS Output Stage Topologies and Output Swing Limitations
  5. 4Example 2: Output Swing Limitations With Instrumentation Amplifiers
  6. 5Summary
  7. 6References

Bipolar and CMOS Output Stage Topologies and Output Swing Limitations

The output swing range of an amplifier is the range of output voltages allowing for linear amplifier operation. As with VCM, the output swing (Vout) limitations are related to operating voltages of transistors in the output stage. Depending on the application and topology, Vout may be more or less limited relative to the rails, regardless whether they are single, dual, or asymmetric. Perfect rail-to-rail performance does not exist in practice, although some of the complimentary MOSFET designs come fairly close.

Many applications require Vout swing to only one rail, typically the negative rail. The earliest op-amp output stages accomplished this by having an NPN emitter-follower configuration with a resistive pull-down (Figure 3-1 A). A pull-down resistor to the negative rail allows the output to approach the negative rail, but this greatly limits the sinking current and results in slow output response. A similar design (bipolar or MOSFET) utilized NPN/NMOS current sources in place of the pull-down resistor, offering higher gain and near to-negative-rail output swing (Figure 3-1 B).

With the advent of modern complimentary bipolar processes, better matched, high speed PNP and NPN transistors became available. As a result, the complimentary emitter-follower output stage (Figure 3-1 C) was developed with its most significant advantage being low output impedance. The major drawback of this topology is its limited output swing, typically on the order of 1V or more to the rail due to transistor operating voltages in the stage. Specifically, the minimal forward-bias voltage across the PNP current source (VFB-P), and the base-emitter voltage (VBE-N) limit swing to positive rail, whereas the VFB-N of the NPN current source and the VBE-P limit swing to negative rail. Full output voltage swing of the complimentary bipolar output stage is thus:

Equation 6. +Vs - Vsat (npn) - Vbe (pnp) > Vout > -Vs + Vsat (pnp) + Vbe (npn)

More recent complimentary common-emitter or common-source output stages (Figure 3-1 D and Figure 3-1 E), allow the op-amp output swing much closer to rail, but both of these stages have fairly high output impedance. For the bipolar version of this stage, the output swing limitation to each rail comes from Vce, (sat), or the minimal collector-emitter voltage needed to keep each transistor operating in the linear region. The typical Vsat for a bipolar transistor is 300mV at 25ºC and changes by roughly -2mV per each ºC increase in temperature.

Equation 7. -Vs + Vsat < Vout < +Vs - Vsat

We can perform a similar analysis to the MOSFET version of this stage, illustrated in Figure 3-1 (E). The output swing limitation comes from the MOSFET on-resistance (Ron) while in the triode region, which causes an output voltage range limitation relative to the rail equal to Id × Ron. In essence, in the non-linear operating region, the MOSFET acts as a small resistor and produces a voltage drop. Under unloaded conditions, Id = Iq, the limitation caused by the voltage drop is on the order of 5 mV to 50mV, which is considered almost truly rail-to rail performance.

Equation 8. -Vs + Id x Ron > Vout > +Vs + Id x Ron

Keep in mind, that under normal operation Id is equal to the quiescent current of the output transistors, Iq, plus the load current. In other words, the output swing will decrease as the load current increases. A plot illustrating this effect is included in data sheets – look for the output voltage swing vs output current plot (often known as a claw curve). Operate within the range of the curves to remain in linear operation

Figure 3-1 Common Output Stage Topologies