SLAAEN0 September   2024 MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Low-Frequency Subsystem Introduction
    1. 2.1 Resetting LFSS IP Using VBAT
    2. 2.2 Power Domain Supply Detection
      1. 2.2.1 Start-Up Sequences
      2. 2.2.2 LFSS IP Behavior
    3. 2.3 LFXT, LFOSC
    4. 2.4 Independent Watchdog Timer (IWDT)
    5. 2.5 Tamper I/O
      1. 2.5.1 IOMUX Mode
      2. 2.5.2 Tamper Mode
        1. 2.5.2.1 Tamper Event Detection
        2. 2.5.2.2 Timestamp Event Output
        3. 2.5.2.3 Heatbeat Generator
    6. 2.6 Scatchpad Memory (SPM)
    7. 2.7 Real-Time Clock (RTC)
    8. 2.8 VBAT Charging Mode
  6. 3Application Examples
    1. 3.1 Tamper I/O Heartbeat Example
    2. 3.2 RTC Tamper I/O Timestamp Event Example
    3. 3.3 Supercapacitor Charging Example
    4. 3.4 LFOSC Transition Back to LFXT Example
    5. 3.5 RTC_A Calibration
      1. 3.5.1 Peripheral ADC 12
      2. 3.5.2 RTC_A

2.6 Scatchpad Memory (SPM)

SPM contains the 16 to 256-byte register-based memory and retains data like flash as long as VBAT is supplied. SPM retains memory when the main VDD power is lost or during shutdown mode. SPM does not retain any memory content if VBAT power is lost. Memory size is from 4 to 64 words of 32-bit size and each bit is addressable for read and write. Figure 2-8 shows the LFSS write enable register is implemented to protect the memory from overwrite.

MSPM0L2228 SPM DiagramFigure 2-8 SPM Diagram