SLAU958A January 2025 – March 2025 MSPM0G3507
Table 5-34 shows the register to configure hardware pins.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-20 | RESERVED | R/W | 0h | Reserved |
| 19 | VDC_FILT_DIS | R/W | 0b | Vdc Filter Disable 0h = Enabled 1h = Disabled |
| 18-3 | RESERVED | R/W | 0h | Reserved |
| 2 | BRAKE_PIN_MODE | R/W | 0b | Brake pin mode 0h = Low side Brake 1h = Align Brake |
| 1-0 | BRAKE_INPUT | R/W | 00b | Brake pin override 0h = Hardware Pin BRAKE 1h = Override pin and brake / align according to BRAKE_PIN_MODE 2h = Override pin and do not brake / align 3h = Hardware Pin BRAKE |