SLUU224A May   2005  – March 2022 TPS40100

 

  1.   Trademarks
  2. 1Introduction
  3. 2Description
    1. 2.1 Applications
    2. 2.2 Features
      1. 2.2.1 Using Remote Sense (J3)
      2. 2.2.2 Simultaneous Tracking (J3)
      3. 2.2.3 Enable (SW2)
      4. 2.2.4 Margin Up/Down (J4)
      5. 2.2.5 Power Good (J1)
      6. 2.2.6 Synchronization (J1)
  4. 3Electrical Performance Specifications
  5. 4Schematic
  6. 5Test Setup
    1. 5.1 Equipment
      1. 5.1.1 Voltage Source (VIN)
      2. 5.1.2 Meters
      3. 5.1.3 Loads (LOAD1)
      4. 5.1.4 Recommended Wire Gauge
      5. 5.1.5 Other
    2. 5.2 Equipment Setup
      1. 5.2.1 Initial EVM Jumper and Switch Settings
      2. 5.2.2 Procedure
      3. 5.2.3 Start-Up and Shutdown Procedure
      4. 5.2.4 Equipment Shutdown
    3. 5.3 Other Tests
      1. 5.3.1 Adjusting Output Voltage (R1 and R3)
      2. 5.3.2 Remote Sense Test Setup
      3. 5.3.3 Voltage Tracking Test Setup
        1. 5.3.3.1 Single Unit Tracking (Charge)
        2. 5.3.3.2 Single Unit Tracking (Discharge)
      4. 5.3.4 Enable and Disable Test Setup
        1. 5.3.4.1 Power-On Enable
      5. 5.3.5 Margin Test Setup
        1. 5.3.5.1 Margin Up 5%
      6. 5.3.6 Power Good and Synchronization Test Setup
        1. 5.3.6.1 Synchronization
  7. 6TPS40100EVM Typical Performance Data and Characteristics Curves
    1. 6.1 Efficiency
    2. 6.2 Line and Load Regulation
    3. 6.3 Loop Stability
  8. 7EVM Assembly Drawings and Layout
  9. 8List of Materials
  10. 9Revision History

EVM Assembly Drawings and Layout

Figure 7-1 through Figure 7-6 show the design of the TPS40100EVM-001 printed circuit board. The EVM has been designed using a 4-layer, 2-oz copper-clad 3.0-inch × 3.25-inch circuit board with most of the components on the top side to allow the user to easily view, probe, and evaluate the TPS40100 control IC in a practical application. Moving components to both sides of the PCB or using additional internal layers can offer additional size reduction for space constrained systems.

GUID-20220228-SS0I-6NRH-GL48-9C2XBMF7TVGN-low.png Figure 7-1 TPS40100EVM-001 Component Placement (Viewed from Top)
GUID-20220228-SS0I-S7BZ-WB7B-BX99XGTPWPBD-low.png Figure 7-2 TPS40100EVM-001 Silkscreen (Viewed from Top)
GUID-20220228-SS0I-4GKX-DFXX-DKKNS4L9HPDK-low.png Figure 7-3 TPS40100EVM-001 Top Copper (Viewed from Top)
GUID-20220228-SS0I-2XCR-8CDJ-7FQNZ0M4FZZ1-low.png Figure 7-4 TPS40100EVM-001 Layer 2 (X-Ray View from Top)
GUID-20220228-SS0I-PXZF-R3BH-RWC1XBPF70KN-low.png Figure 7-5 TPS40100EVM-001 Layer 3 (X-Ray View from Top)
GUID-20220228-SS0I-QVLG-SZBB-4SQC3RBVQXTW-low.png Figure 7-6 TPS40100EVM-001 Bottom Copper (X-Ray View from Top)