The large thermal dissipation that a High Side Switch sustains during capacitive inrush can exceed the average power dissipation of the device calculated in Power Dissipation Calculation. This leads to relibaility concerns if device junction temperatures rise above T_j(Max) and possibly cause the device to go into Over Temperature Shutdown.

For average power consumption, we had estimated junction temperature as in Equation 4. Capacitive inrush events, however, are not steady-state conditions and are short in duration. A high-side switch may be able to tolerate higher-than-average power dissipation for short periods during inrush events due to the input-dependent thermal impedance.

Transient thermal impedance is typically modeled via a Foster RC network, shown in Figure 3-13. This model links the high-side switch junction temperature T_J to ambient temperature T_A and the response of the thermal RC network to power dissipated in the device P_DIS. The thermal impedance values in the model are strongly dependent on device construction and packaging. Z_ΘJA is defined as in Equation 25.

This model shows us that short bursts of power have less effect on the junction temperature if the period is much less than the RC time constant, acting as a high-pass filter. For long periods of time, the thermal capacitances block the power and all the power passes through the thermal resistances R_1,2,3..n. The sum of these thermal resistances in the model is R_ΘJA, which is specified in the device data sheets. The modeled response to a fast power transient is compared to a steady-state power dissipation in Figure 3-13.

During capacitive inrush, Z_ΘJA, P_DIS, and T_J are functions of time during, as shown in Figure 3-13. Time is on a logarithmic scale, and Z_ΘJA is the time dependent thermal impedance of the device (between junction and ambient air). Z_ΘJA follows an exponential decay according to the time constants of the Foster model for a particular device.

Z_ΘJA is monotonically increasing during the inrush period, Δt, but total power dissipated in the device is dropping linearly due to current limiting. The peak power dissipation I_LIM·V_SUP occurs at the beginning of this period, while Z_ΘJA, the sum of decaying exponentials, peaks at the end of the inrush period.

This converse relationship causes junction temperature to peak at approximately half of the inrush period, or at Δt/2. This holds true as long the inrush period Δt is less than the effective thermal time constant of the device, or before Z_ΘJA plots flatten out. This is around 500 s for most high-side switches.

Mathematically, junction temperature is the convolution of Z_ΘJA and P_DIS, which are both time variant, shown in Equation 26. Evaluating this convolution to find ΔT_j is exceedingly difficult, and is best left to simulators like PSPICE if the device has a thermal-enabled model available.

For design purposes, we are mainly concerned with finding T_JMax) during the inrush period rather than obtaining an expression for T_J for any point in time. This simplification allows us approximate T_J(Max) as in Equation 27. In Equation 27, Z_ΘJA(Δt/2) is the transient thermal impedance at half of the inrush period Δt calculated as in Equation 24. Then we find Z_ΘJA at Δt/2 from the device's transient thermal impedance curve, as shown in Figure 3-16.

Figures for transient thermal impedance Z_ΘJA are located in Appendix A and provided for each TI high-side switch listed in Table 3-1.

Equation 27 is accurate to within ±10% of PSPICE simulation results for T_J(Max), but only for inrush times Δt < ~500 s, or the point at which the Z_ΘJA curve flattens. Beyond this point, this approximation begins to undershoot as peak temperature occurs later than Δt/2. A more advanced thermal simulation with PSPICE, Simulink, or another modeling tool should be used at that point.

This procedure can be repeated for multi-channel devices using the transient thermal data Z_ΘJA for 2 or 4-Ch ON. However, this data should only be used for situations where both channels turn on simulatenously and the loading conditions are identical.

Adding on to our examples for TPS2H160-Q1, we can estimate T_J(Max) during capacitive inrush. In this example, a single channel drives a 470-µF capacitive load, current limit I_LIM is set to 1 A, supply voltage is 24 V, and the ambient temperature is T_A = 25°C.

From Equation 18, we found the inrush period lasts Δt = 11.28 ms. Referencing the data for TPS2H160-Q1 in Appendix A, we can draw a line at Δt = 11.28 ms as in Figure 3-16 to find the values of R_ΘJA at half the inrush period Δt since we are only driving on one channel, Z_ΘJA(Δt/2) = 5.4°C/W.

Current limiting is active during the inrush period and is responsible for significant power dissipation in the high-side switch. This is because current limiting is achieved through control of the FET R_ON. R_ON must be forced up to several orders of magnitude higher than the data sheet specification a the beginning of inrush, which leads to high I²R losses in the FET channel.

Once the device turns on the FET, V_DS across the fet is initially V_SUP and reduces to nearly 0 V once the capacitor load is charged. This initial point is where the peak power dissipation occurs. In our example with TPS2H160-Q1, we had set ILIM = 1 A, so the peak power is 24 V·1 A = 24W. We can now calculate T_J(MAX) during inrush by substituting our values for V_SUP, I_LIM, T_A, and Z_ΘJA(Δt/2) into Equation 27, shown in Equation 28.

From Equation 28, we find that the T_J(Max) ≈ 111°C at an ambient temperature of 25°C. and 111°C < 150°C, well within the specification limits for T_J. Our ΔT_J from ambient is therefore 86°C.

As this is an estimate and operating conditions may vary from the design point, it is recommended to allow for sufficient headroom between T_J(Max) and 150°C. Not properly limiting T_J may trigger over-temperature shutdown and reduce both reliability and device lifetime.

In addition to keeping T_J < 150°C, it is recommended to keep ΔT_J < T_SW, where T_SW = 60°C to prevent thermal swing shutdown during inrush. As the highest temperature will occur in the FET junction during inrush, designing for ΔT_J < T_SW guarantees thermal swing shutdown will not be triggered during inrush. Since T_FET T_CON are strongly time-depenedent on loading conditions over inrush, ΔT_J could also potentially be larger than T_SW without triggering thermal swing shutdown.

For the most accurate thermal results, it is strongly recommended to use thermal-enabled PSPICE models for TI's high-side switches which model T_J, T_CON, and thermal shutdown. For more information on simulating device thermals in PSPICE, please see Using PSpice Simulator to Model Thermal Behavior in TI’s Smart High-Side Switches.