SLVAFP8 December   2023 AM625SIP , TPS65219

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 TPS65219 Overview
    1. 2.1 TPS65219 Functional Block Diagram
  6. 3 TPS65219 Variants
    1. 3.1 TPS65219 NVMs to Power AM625SIP
  7. 4 TPS6521905 User-Programmable NVM
  8. 5 AM62x Core Voltage Selection
  9. 6 VSYS Voltage Ramp
  10. 7 Power Block Diagrams
    1. 7.1 TPS6521902 Powering AM62x
    2. 7.2 TPS6521908 Powering AM62x
  11. 8 TPS65219 VS Discrete
  12. 9 Summary
  13. 10References

6 VSYS Voltage Ramp

The TPS65219 power-up sequence is gated by the following main steps: Voltage on VSYS goes above the POR_Rising threshold, PMIC loads the NVM content into the register map and then waits for an ON request before executing the power-up sequence. The first ON request can be bypassed by enabling the first supply detection feature (FSD) in the PU_ON_FSD register field. When PU_ON_FSD=0x1, PMIC starts executing the power-up sequence after the NVM settings are loaded to the register map, without waiting for an ON request. In this scenario, customers must ensure the pre-regulator supplying the VSYS reaches a stable output voltage before the PMIC starts executing the power-up sequence. The voltage on VSYS must reach the targeted Vout in approximately 2.3ms after VSYS goes above the POR_threshold.

Note: If FSD is enabled (PU_ON_FSD=0x1) and VSYS has a slow ramp, PMIC will try to enable the first rail without having the required input to output voltage headroom. This conditions create a fault on the PMIC.

Figure 6-1 shows an example where FSD is enabled and VSYS has a slow ramp.

GUID-D089AFEB-E634-4400-9E9A-B8B0D4C7C620-low.svgFigure 6-1 VSYS Slow Ramp with FSD Enabled
  • Step 1: VSYS reaches the POR_Rising threshold.
  • Step 2: NVM settings are loaded to the registers in approximately 2.3ms.
  • Step 3: Since FSD is enabled, PMIC starts executing the power-up sequence but the voltage on VSYS is still too low and does not meet the input to output headroom. The first PMIC rail in the power-up sequence shows three voltage peaks which represent the first power-up and the two attempts configured in the retry counter (MASK_RETRY_COUNT).
  • Step 4: the enable pin goes high and the pin deglitch takes effect.
  • Step 5: the PMIC is not able to execute the power-up sequence because the device stayed in Initialize state after the power-up attempts in step#3. A power-cycle on VSYS with a faster ramp is required to get the PMIC out of the Initialize state.

Figure 6-2 shows an example where FSD is disabled and VSYS has a slow ramp.

GUID-998AB172-5CD4-409D-922C-23415069062D-low.svg
  • Step 1: VSYS reaches the POR_Rising threshold.
  • Step 2: NVM settings are loaded to the registers in approximately 2.3ms.
  • Step 3: Since FSD is disabled, PMIC waits for an ON request to execute the power-up sequence.
  • Step 4: the enable pin goes high and the pin deglitch takes effect.
  • Step 5: the PMIC starts executing the power-up sequence starting with the rails assigned to the first slot.
Figure 6-2 VSYS Slow Ramp with FSD Disabled