SLVUBQ1A August 2020 – May 2021 TPS543620
Figure 3-1 through Figure 3-5 show the efficiency for both designs on the TPS543620EVM. Using the selection jumpers for U2, the results for different output voltage and switching frequency combinations are included. The test points listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
|RELATED IC||TEST POINT NAME||REFERENCE DESIGNATOR||FUNCTION|
|U1||VIN_U1||TP1||Input voltage test point connected near pins of U1|
|VOUT_U1||TP2||Output voltage test point near output inductor of U1|
|PGND_EFF_U1||TP5||PGND reference test point for both input and output voltages Kelvin connected near U1|
|U2||VIN_U2||TP12||Input voltage test point connected near pins of U2|
|VOUT_U2||TP15||Output voltage test point near output inductor of U2|
|PGND_EFF_U2||TP17||PGND reference test point for both input and output voltages Kelvin connected near U2|
|VOUT = 1 V||fSW = 1500 kHz|
|VIN = 12 V||fSW = 1000 kHz|
|VIN = 9 V||VOUT = 1 V||RMODE = 60.4 kΩ|
|VOUT = 1 V||fSW = 1000 kHz|
|VIN = 9 V||VOUT = 1 V|