SNLA261A August   2016  – March 2024 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I , DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM

 

  1.   1
  2.   DP838xx Wake-On-LAN
  3.   Trademarks
  4. 1Introduction
  5. 2Wake-on-LAN
    1. 2.1 WoL – Principles of Operation
      1. 2.1.1 Magic Packet Detection
      2. 2.1.2 Magic Packet Detection with Secure-ON
      3. 2.1.3 Custom Pattern Detection
      4. 2.1.4 WoL - Mechanisms
    2. 2.2 WoL - Implementation
      1. 2.2.1 Magic Packet Detection - Implementation
        1. 2.2.1.1 Example 1 – Pulse Mode Indication on LED_1 (DP83822)
        2. 2.2.1.2 Example 2 – Level Change Mode Indication on COL (DP83822)
        3. 2.2.1.3 Example 3 – Pulse Mode indication on GPIO_1 (DP83867)
      2. 2.2.2 Magic Packet Detection with Secure-ON - Implementation
        1. 2.2.2.1 Example 1 – Pulse Mode Indication on COL with Secure-ON (DP83822)
        2. 2.2.2.2 Example 2 – Level Change Mode Indication on RX_D3 with Secure-ON (DP83822)
        3. 2.2.2.3 Example 3 – Pulse Mode indication on GPIO_1 (DP83869)
      3. 2.2.3 Custom Pattern Detection - Implementation
        1. 2.2.3.1 Example 1 – Pulse Mode Indication on COL with Byte Mask (DP83822)
        2. 2.2.3.2 Example 2 – Pulse Mode Indication on GPIO_0 with Byte Mask (DP83867)
  6. 3Summary
  7. 4Revision History

2.1.4 WoL - Mechanisms

When the appropriate WoL pattern has been properly received by the PHY, there is configurability for the trigger generated by the PHY. System designs have the option to have the trigger be a pulse waveform as long as 8, 16, 32, or 64 cycles of a 125MHz clock, or be a latch-able level change which can cause the PHY to generate a high signal. The signal's latch can only be cleared by writing to a field to clear.

In Figure 2-2, the PHY is set to output a pulse with 256.3ns long. This is equivalent to 32 periods of a 125MHz waveform.

GUID-20240227-SS0I-1ZFH-WXKS-2TWMKDVRMBTV-low.svg Figure 2-2 WoL Mechanism - 32 Clock Cycle

In Figure 2-3, the PHY is set to output a pulse with 512.4ns long. This is equivalent to 64 periods of a 125MHz waveform.

GUID-20240227-SS0I-MWSJ-WSDN-DDRLNNRBZ2CX-low.svg Figure 2-3 WoL Mechanism - 64 Clock Cycle

In Figure 2-4, the PHY is set to a level change upon receipt of the appropriate frame. This level change is active high and can only be cleared with a register write to the WoL configuration register.

GUID-20240227-SS0I-4MFC-FRXT-GBWR6T1R1PM7-low.svg Figure 2-4 WoL Mechanism - Level