SNLA261A August 2016 – March 2024 DP83822H , DP83822HF , DP83822I , DP83822IF , DP83825I , DP83826E , DP83826I , DP83867CR , DP83867CS , DP83867E , DP83867IR , DP83867IS , DP83869HM
WoL Magic Packet detection requires use of the following registers:
Register Name | DP8382x Address | DP8386x Address |
---|---|---|
Receive Configuration Register | Reg 0x4A0 | Reg 0x134 |
Receive Status Register | Reg 0x4A1 | Reg 0x135 |
MAC Destination Address Registers | Reg 0x4A2-0x4A4 | Reg 0x136-0x138 |
While these registers are common to the DP8382x and DP8386x families, please consult PHY's individual data sheet for configuring specific GPIO pins for WoL with registers.
Examples Table 2-8 and Table 2-4 are intended to display various configuration options for DP8382x WoL Magic Packet detection feature.
For all examples below, the first byte (0) as listed in data sheet is the left-most byte. IE if pattern is "A1-C3-D7-AB-CD-FC-87", the first byte is A1, not 87.