SNLA491 August   2025 DP83826AE , DP83826AI

 

  1.   1
  2.   Trademarks
  3. 1DP83826A Application Overview
  4. 2Troubleshooting the Application
    1. 2.1 Schematic and Layout Checklist
    2. 2.2 Device Health Checks
      1. 2.2.1 Voltage Checks
      2. 2.2.2 Probe the RESET_N Signal
      3. 2.2.3 Probe RBIAS and CEXT
      4. 2.2.4 Probe the XI Clock
      5. 2.2.5 Probe the Strap Pins During Initialization
      6. 2.2.6 Probe the Serial Management Interface Signals (MDC, MDIO)
        1. 2.2.6.1 Read and Check Register Values
          1. 2.2.6.1.1 Extended Register Access
    3. 2.3 MDI Health Checks
      1. 2.3.1 Magnetics
      2. 2.3.2 Probe the MDI Signals
      3. 2.3.3 Link Quality Check
      4. 2.3.4 Compliance
    4. 2.4 MII Health Checks
      1. 2.4.1 MII Check
      2. 2.4.2 RMII Check
    5. 2.5 Loopback and PRBS
      1. 2.5.1 Loopback Modes
      2. 2.5.2 Transmitting and Receiving Packets With the MAC
      3. 2.5.3 Transmitting and Receiving Packets With BIST
  5. 3Summary
  6. 4References

2.2.4 Probe the XI Clock

The following guidelines are the main specifications to reference for compatible crystals.

Table 2-2 25MHz Crystal Specifications
PARAMETERTEST CONDITIONMINTYPMAXUNIT
Frequency25MHz
Frequency ToleranceOperational Temperature-100100ppm
Load Capacitance1540pF
ESR50Ω
Table 2-3 25MHz Oscillator Specifications
PARAMETERTEST CONDITIONMINTYPMAXUNIT
Frequency25MHz
Frequency ToleranceOperational Temperature±50ppm
Frequency Stability1 year aging±50ppm
Rise / Fall Time20% - 80%5ns
SymmetryDuty Cycle40%60%
Jitter RMSIntegration Band: 12kHz to 5MHz11ps

Verify the frequency and signal integrity. For link integrity the refernce clock must be:

  • MII and RMII leader modes
    • 25MHz ±50ppm
  • RMII follower mode
    • 50MHz ±50ppm

If using a crystal as the clock source, the recommendation is to probe the CLK_OUT signal. Probing on the crystal nodes can change the capacitive loading and therefore change the operational frequency.

Note: For more information on designing with a crystal network, please refer to Selection and specification of crystals for Texas Instruments ethernet physical layer transceivers, application note.

The default signal on CLK_OUT is a buffered version of the XI reference and will provide a representative measurement. If CLK_OUT is either not available due to strapping or is unexpectedly absent, XI pin can have to be probed but results must be taken lightly.