SNVU596A October 2018 – July 2025 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1
Using the setup described in Section 2 allows the MCU to easily configure the LP8752x-Q1 PMIC after a power-on reset, or after any event causing a register reset. To make sure that this is done correctly, follow the sequence described in this section. The following list shows the actions to take to make sure the LP8752x-Q1 PMIC is configured correctly. These actions must be taken after a power-on reset or a register reset.
Upon a power-on reset, waiting for the nINT line to be set low makes sure that the PMIC is ready for I2C communication. Waiting for the nINT line to be set low at any other time allows the PMIC to know when a register reset has occurred. The timing diagrams in Figure 3-1, Figure 3-2, and Figure 3-3 show how to configure the LP8752x-Q1 PMIC after a power-on reset or register reset has occurred. Once all of the I2C writes are finished, the MCU clears the interrupt and enables the PMIC. The MCU can do this by writing a 1 to the RESET_REG bit to clear the interrupt and by pulling the ENx pin high to turn on the PMIC outputs.
Figure 3-1 Configuration Sequence During
Startup (RESET_REG_MASK = 0)