SNVU596A October   2018  – July 2025 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

Configuration Sequence

Using the setup described in Section 2 allows the MCU to easily configure the LP8752x-Q1 PMIC after a power-on reset, or after any event causing a register reset. To make sure that this is done correctly, follow the sequence described in this section. The following list shows the actions to take to make sure the LP8752x-Q1 PMIC is configured correctly. These actions must be taken after a power-on reset or a register reset.

  1. Power on PMIC. (VVANA > VANAUVLO)
  2. Set NRST high
  3. Wait for 1.2ms (or for nINT line to be set low, if RESET_REG_MASK = 0)
  4. Set new configuration using I2C communication in recommended order. See Section 3.3.
    1. Voltage settings
    2. Regulator settings
    3. GPIO settings
    4. Clock sync functions
    5. PGOOD settings
    6. Interrupt settings
    7. Startup / shutdown settings
    8. Set ENx pin control bits
    9. Set EN_BUCKx bits
  5. Clear Interrupts.
  6. Set ENx pin high to startup sequence.

Upon a power-on reset, waiting for the nINT line to be set low makes sure that the PMIC is ready for I2C communication. Waiting for the nINT line to be set low at any other time allows the PMIC to know when a register reset has occurred. The timing diagrams in Figure 3-1, Figure 3-2, and Figure 3-3 show how to configure the LP8752x-Q1 PMIC after a power-on reset or register reset has occurred. Once all of the I2C writes are finished, the MCU clears the interrupt and enables the PMIC. The MCU can do this by writing a 1 to the RESET_REG bit to clear the interrupt and by pulling the ENx pin high to turn on the PMIC outputs.

LP8756210-Q1 LP875220-Q1 LP875230-Q1 LP875240-Q1 LP875250-Q1 Configuration Sequence During
                    Startup (RESET_REG_MASK = 0) Figure 3-1 Configuration Sequence During Startup (RESET_REG_MASK = 0)
LP8756210-Q1 LP875220-Q1 LP875230-Q1 LP875240-Q1 LP875250-Q1 Configuration Sequence During
                    Startup (RESET_REG_MASK = 1) Figure 3-2 Configuration Sequence During Startup (RESET_REG_MASK = 1)
LP8756210-Q1 LP875220-Q1 LP875230-Q1 LP875240-Q1 LP875250-Q1 Configuration Sequence During
                    Reset Figure 3-3 Configuration Sequence During Reset