SNVU596A October   2018  – July 2025 LP87521-Q1 , LP87522-Q1 , LP87523-Q1 , LP87524-Q1 , LP87525-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Setup
    1. 2.1 SCL/SDA Pins
    2. 2.2 NRST Pin
    3. 2.3 ENx (GPIOx) Pins
    4. 2.4 nINT
  6. 3Configuration
    1. 3.1 Configuration Sequence
    2. 3.2 Default OTP Configurations
    3. 3.3 Recommended Order of Configuring Registers Through I2C
      1. 3.3.1 Voltage Settings
      2. 3.3.2 Other Regulator Settings
      3. 3.3.3 GPO Settings
      4. 3.3.4 Clock Sync Functions
      5. 3.3.5 PGOOD Settings
      6. 3.3.6 Interrupt Settings
      7. 3.3.7 Startup and Shutdown Sequence
      8. 3.3.8 Set ENx Pin Control Bits
      9. 3.3.9 Set EN_BUCKx Bits
  7. 4Revision History

2.2 NRST Pin

The NRST pin (pin 20) is used to reset the device logic/enable device internal logic and IO interface. When the NRST voltage is below threshold level all power switches, references, controls, and bias circuitry of the LP8752x-Q1 device are turned off. When NRST is set to high level (and VANA is above UVLO level) this initiates power-on-reset (POR), OTP reading and enables the system I/O interface. The I2C host must allow at least 1.2ms before writing or reading data to the LP8752x-Q1. Device enters STANDBY-mode after internal startup sequence. The host can change the default register setting by I2C if needed. The regulator(s) can be enabled/disabled by ENx pin(s) or by I2C interface.