SPRACU5C June 2021 – September 2023 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
The active high ready / active low busy (R/B#) output from the NAND flash is open drain and is connected to the GPMC0_WAIT0 and GPMC0_WAIT1 signals (depending on the configuration). It is recommended to provide pullup resistor (recommended value is 4.7 kΩ) connected to the peripheral specific Dual-voltage IO supply rail. Place the pullup resistor close to the device pin.
It is recommended to provision for external pullup resistors on GPMC0_CSn0..3 (depending on the configuration) to hold the signal high when processor is held in reset, or after reset, before software has configured the PADCONFIG registers to enable the Tx buffer.
Provide series resistor (22 Ω) (close to processor pin) for GPMC0_CLK.